drivers/spi/spi-pic32.c

123 static inline void pic32_spi_enable(struct pic32_spi *pic32s)
125 	writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
128 static inline void pic32_spi_disable(struct pic32_spi *pic32s)
130 	writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
136 static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
141 	div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
143 	writel(div & BAUD_MASK, &pic32s->regs->baud);
146 static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
148 	u32 sr = readl(&pic32s->regs->status);
153 static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
155 	u32 sr = readl(&pic32s->regs->status);
161 static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
165 	tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
166 	tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
170 	 * though to use (pic32s->fifo_n_byte - rxfl - txfl) as
176 	rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
177 		    (pic32s->tx_end - pic32s->tx)) / n_bytes;
178 	return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
182 static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
184 	u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
186 	return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
190 static void pic32_spi_rx_##__name(struct pic32_spi *pic32s)	\
193 	u32 mx = pic32_rx_max(pic32s, sizeof(__type));		\
195 		v = read##__bwl(&pic32s->regs->buf);		\
196 		if (pic32s->rx_end - pic32s->len)		\
197 			*(__type *)(pic32s->rx) = v;		\
198 		pic32s->rx += sizeof(__type);			\
202 static void pic32_spi_tx_##__name(struct pic32_spi *pic32s)	\
205 	u32 mx = pic32_tx_max(pic32s, sizeof(__type));		\
208 		if (pic32s->tx_end - pic32s->len)		\
209 			v = *(__type *)(pic32s->tx);		\
210 		write##__bwl(v, &pic32s->regs->buf);		\
211 		pic32s->tx += sizeof(__type);			\
219 static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
222 	disable_irq_nosync(pic32s->fault_irq);
223 	disable_irq_nosync(pic32s->rx_irq);
224 	disable_irq_nosync(pic32s->tx_irq);
227 	dev_err(&pic32s->host->dev, "%s\n", msg);
228 	if (pic32s->host->cur_msg)
229 		pic32s->host->cur_msg->status = -EIO;
230 	complete(&pic32s->xfer_done);
235 	struct pic32_spi *pic32s = dev_id;
238 	status = readl(&pic32s->regs->status);
242 		writel(STAT_RX_OV, &pic32s->regs->status_clr);
243 		writel(STAT_TX_UR, &pic32s->regs->status_clr);
244 		pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n");
249 		pic32_err_stop(pic32s, "err_irq: frame error");
253 	if (!pic32s->host->cur_msg) {
254 		pic32_err_stop(pic32s, "err_irq: no mesg");
263 	struct pic32_spi *pic32s = dev_id;
265 	pic32s->rx_fifo(pic32s);
268 	if (pic32s->rx_end == pic32s->rx) {
270 		disable_irq_nosync(pic32s->fault_irq);
271 		disable_irq_nosync(pic32s->rx_irq);
274 		complete(&pic32s->xfer_done);
282 	struct pic32_spi *pic32s = dev_id;
284 	pic32s->tx_fifo(pic32s);
287 	if (pic32s->tx_end == pic32s->tx)
288 		disable_irq_nosync(pic32s->tx_irq);
295 	struct pic32_spi *pic32s = data;
297 	complete(&pic32s->xfer_done);
300 static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
303 	struct spi_controller *host = pic32s->host;
334 	desc_rx->callback_param = pic32s;
357 static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
360 	struct spi_controller *host = pic32s->host;
366 	cfg.src_addr = pic32s->dma_base + buf_offset;
367 	cfg.dst_addr = pic32s->dma_base + buf_offset;
368 	cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */
369 	cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */
388 static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
395 		pic32s->rx_fifo = pic32_spi_rx_byte;
396 		pic32s->tx_fifo = pic32_spi_tx_byte;
401 		pic32s->rx_fifo = pic32_spi_rx_word;
402 		pic32s->tx_fifo = pic32_spi_tx_word;
407 		pic32s->rx_fifo = pic32_spi_rx_dword;
408 		pic32s->tx_fifo = pic32_spi_tx_dword;
418 	pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte,
421 	v = readl(&pic32s->regs->ctrl);
424 	writel(v, &pic32s->regs->ctrl);
427 	if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
428 		pic32_spi_dma_config(pic32s, dmawidth);
435 	struct pic32_spi *pic32s = spi_controller_get_devdata(host);
437 	pic32_spi_enable(pic32s);
445 	struct pic32_spi *pic32s = spi_controller_get_devdata(host);
450 	if (pic32s->bits_per_word != spi->bits_per_word) {
451 		pic32_spi_set_word_size(pic32s, spi->bits_per_word);
452 		pic32s->bits_per_word = spi->bits_per_word;
456 	if (pic32s->speed_hz != spi->max_speed_hz) {
457 		pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz);
458 		pic32s->speed_hz = spi->max_speed_hz;
462 	if (pic32s->mode != spi->mode) {
463 		val = readl(&pic32s->regs->ctrl);
477 		writel(val, &pic32s->regs->ctrl);
478 		pic32s->mode = spi->mode;
488 	struct pic32_spi *pic32s = spi_controller_get_devdata(host);
492 	       test_bit(PIC32F_DMA_PREP, &pic32s->flags);
499 	struct pic32_spi *pic32s;
504 	pic32s = spi_controller_get_devdata(host);
508 	    (transfer->bits_per_word != pic32s->bits_per_word)) {
509 		ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word);
512 		pic32s->bits_per_word = transfer->bits_per_word;
516 	if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) {
517 		pic32_spi_set_clk_rate(pic32s, transfer->speed_hz);
518 		pic32s->speed_hz = transfer->speed_hz;
521 	reinit_completion(&pic32s->xfer_done);
525 		ret = pic32_spi_dma_transfer(pic32s, transfer);
535 		pic32s->tx = (const void *)transfer->tx_buf;
536 		pic32s->rx = (const void *)transfer->rx_buf;
537 		pic32s->tx_end = pic32s->tx + transfer->len;
538 		pic32s->rx_end = pic32s->rx + transfer->len;
539 		pic32s->len = transfer->len;
542 		enable_irq(pic32s->fault_irq);
543 		enable_irq(pic32s->rx_irq);
544 		enable_irq(pic32s->tx_irq);
548 	time_left = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ);
572 	struct pic32_spi *pic32s = spi_controller_get_devdata(host);
574 	pic32_spi_disable(pic32s);
606 static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
608 	struct spi_controller *host = pic32s->host;
633 	if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE))
637 	set_bit(PIC32F_DMA_PREP, &pic32s->flags);
655 static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
657 	if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags))
660 	clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
661 	if (pic32s->host->dma_rx)
662 		dma_release_channel(pic32s->host->dma_rx);
664 	if (pic32s->host->dma_tx)
665 		dma_release_channel(pic32s->host->dma_tx);
668 static void pic32_spi_hw_init(struct pic32_spi *pic32s)
673 	pic32_spi_disable(pic32s);
675 	ctrl = readl(&pic32s->regs->ctrl);
678 	pic32s->fifo_n_byte = 16;
700 	writel(ctrl, &pic32s->regs->ctrl);
704 	writel(ctrl, &pic32s->regs->ctrl2_set);
708 			      struct pic32_spi *pic32s)
713 	pic32s->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
714 	if (IS_ERR(pic32s->regs))
715 		return PTR_ERR(pic32s->regs);
717 	pic32s->dma_base = mem->start;
720 	pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
721 	if (pic32s->fault_irq < 0)
722 		return pic32s->fault_irq;
724 	pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
725 	if (pic32s->rx_irq < 0)
726 		return pic32s->rx_irq;
728 	pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
729 	if (pic32s->tx_irq < 0)
730 		return pic32s->tx_irq;
733 	pic32s->clk = devm_clk_get_enabled(&pdev->dev, "mck0");
734 	if (IS_ERR(pic32s->clk)) {
736 		ret = PTR_ERR(pic32s->clk);
740 	pic32_spi_hw_init(pic32s);
752 	struct pic32_spi *pic32s;
755 	host = spi_alloc_host(&pdev->dev, sizeof(*pic32s));
759 	pic32s = spi_controller_get_devdata(host);
760 	pic32s->host = host;
762 	ret = pic32_spi_hw_probe(pdev, pic32s);
769 	host->max_speed_hz	= clk_get_rate(pic32s->clk);
783 	ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
787 	if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
790 	init_completion(&pic32s->xfer_done);
791 	pic32s->mode = -1;
794 	irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN);
795 	ret = devm_request_irq(&pdev->dev, pic32s->fault_irq,
797 			       dev_name(&pdev->dev), pic32s);
799 		dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq);
804 	irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN);
805 	ret = devm_request_irq(&pdev->dev, pic32s->rx_irq,
807 			       dev_name(&pdev->dev), pic32s);
809 		dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq);
814 	irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN);
815 	ret = devm_request_irq(&pdev->dev, pic32s->tx_irq,
817 			       dev_name(&pdev->dev), pic32s);
819 		dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq);
830 	platform_set_drvdata(pdev, pic32s);
835 	pic32_spi_dma_unprep(pic32s);
843 	struct pic32_spi *pic32s;
845 	pic32s = platform_get_drvdata(pdev);
846 	pic32_spi_disable(pic32s);
847 	pic32_spi_dma_unprep(pic32s);