drivers/spi/spi-pic32-sqi.c

139 	void __iomem		*regs;
173 	val = readl(sqi->regs + PESQI_CLK_CTRL_REG);
177 	writel(val, sqi->regs + PESQI_CLK_CTRL_REG);
180 	return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val,
188 	writel(mask, sqi->regs + PESQI_INT_ENABLE_REG);
190 	writel(mask, sqi->regs + PESQI_INT_SIGEN_REG);
195 	writel(0, sqi->regs + PESQI_INT_ENABLE_REG);
196 	writel(0, sqi->regs + PESQI_INT_SIGEN_REG);
204 	enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
205 	status = readl(sqi->regs + PESQI_INT_STAT_REG);
235 	writel(enable, sqi->regs + PESQI_INT_ENABLE_REG);
324 	pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
326 	pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
371 			val = readl(sqi->regs + PESQI_CONF_REG);
378 			writel(val, sqi->regs + PESQI_CONF_REG);
403 	writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG);
410 	writel(val, sqi->regs + PESQI_BD_CTRL_REG);
425 	writel(0, sqi->regs + PESQI_BD_CTRL_REG);
447 	pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
449 	pic32_clrbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
519 	writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG);
522 	readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val,
532 	val = readl(sqi->regs + PESQI_CMD_THRES_REG);
536 	writel(val, sqi->regs + PESQI_CMD_THRES_REG);
538 	val = readl(sqi->regs + PESQI_INT_THRES_REG);
542 	writel(val, sqi->regs + PESQI_INT_THRES_REG);
545 	val = readl(sqi->regs + PESQI_CONF_REG);
550 	writel(val, sqi->regs + PESQI_CONF_REG);
560 	writel(val, sqi->regs + PESQI_CONF_REG);
563 	writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG);
582 	sqi->regs = devm_platform_ioremap_resource(pdev, 0);
583 	if (IS_ERR(sqi->regs)) {
584 		ret = PTR_ERR(sqi->regs);