drivers/spi/spi-omap2-mcspi.c

115 	struct list_head cs;
165 	struct omap2_mcspi_cs	*cs = spi->controller_state;
167 	writel_relaxed(val, cs->base +  idx);
172 	struct omap2_mcspi_cs	*cs = spi->controller_state;
174 	return readl_relaxed(cs->base + idx);
179 	struct omap2_mcspi_cs *cs = spi->controller_state;
181 	return cs->chconf0;
186 	struct omap2_mcspi_cs *cs = spi->controller_state;
188 	cs->chconf0 = val;
225 	struct omap2_mcspi_cs *cs = spi->controller_state;
228 	l = cs->chctrl0;
233 	cs->chctrl0 = l;
234 	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
308 	struct omap2_mcspi_cs *cs = spi->controller_state;
318 		bytes_per_word = mcspi_bytes_per_word(cs->word_len);
457 	struct omap2_mcspi_cs	*cs = spi->controller_state;
458 	void __iomem		*chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
473 	word_len = cs->word_len;
594 	struct omap2_mcspi_cs	*cs = spi->controller_state;
609 	if (cs->word_len <= 8) {
612 	} else if (cs->word_len <= 16) {
623 	cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
624 	cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
678 			chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
702 	struct omap2_mcspi_cs	*cs = spi->controller_state;
705 	void __iomem		*base = cs->base;
713 	word_len = cs->word_len;
911 	struct omap2_mcspi_cs *cs = spi->controller_state;
922 	cs->word_len = word_len;
974 		cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
975 		cs->chctrl0 |= extclk << 8;
976 		mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
991 	cs->mode = spi->mode;
1056 	struct omap2_mcspi_cs	*cs;
1060 		cs = spi->controller_state;
1061 		list_del(&cs->node);
1063 		kfree(cs);
1073 	struct omap2_mcspi_cs	*cs = spi->controller_state;
1075 	if (!cs) {
1076 		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1077 		if (!cs)
1079 		cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
1080 		cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
1081 		cs->mode = 0;
1082 		cs->chconf0 = 0;
1083 		cs->chctrl0 = 0;
1084 		spi->controller_state = cs;
1086 		list_add_tail(&cs->node, &ctx->cs);
1152 	struct omap2_mcspi_cs		*cs;
1160 	cs = spi->controller_state;
1165 	 * it will be different from cs->mode (the current hardware setup).
1170 	if (spi->mode != cs->mode)
1201 		if (t->len > ((cs->word_len + 7) >> 3))
1219 			writel_relaxed(0, cs->base
1263 	struct omap2_mcspi_cs	*cs;
1326 	list_for_each_entry(cs, &ctx->cs, node) {
1327 		if (msg->spi->controller_state == cs && !mcspi->use_multi_mode) {
1331 		if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1332 			cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1333 			writel_relaxed(cs->chconf0,
1334 					cs->base + OMAP2_MCSPI_CHCONF0);
1335 			readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1415 	struct omap2_mcspi_cs *cs;
1426 	list_for_each_entry(cs, &ctx->cs, node) {
1431 		if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1432 			cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1433 			writel_relaxed(cs->chconf0,
1434 				       cs->base + OMAP2_MCSPI_CHCONF0);
1435 			cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1436 			writel_relaxed(cs->chconf0,
1437 				       cs->base + OMAP2_MCSPI_CHCONF0);
1439 			writel_relaxed(cs->chconf0,
1440 				       cs->base + OMAP2_MCSPI_CHCONF0);
1519 		of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1544 	INIT_LIST_HEAD(&mcspi->ctx.cs);