drivers/spi/spi-mt65xx.c

272 	u32 reg_val;
275 	reg_val = readl(mdata->base + SPI_CMD_REG);
276 	reg_val |= SPI_CMD_RST;
277 	writel(reg_val, mdata->base + SPI_CMD_REG);
279 	reg_val = readl(mdata->base + SPI_CMD_REG);
280 	reg_val &= ~SPI_CMD_RST;
281 	writel(reg_val, mdata->base + SPI_CMD_REG);
291 	u32 reg_val;
310 		reg_val = readl(mdata->base + SPI_CFG0_REG);
314 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
315 				reg_val |= (((hold - 1) & 0xffff)
320 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
321 				reg_val |= (((setup - 1) & 0xffff)
327 				reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
328 				reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
332 				reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
333 				reg_val |= (((setup - 1) & 0xff)
337 		writel(reg_val, mdata->base + SPI_CFG0_REG);
342 		reg_val = readl(mdata->base + SPI_CFG1_REG);
343 		reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
344 		reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
345 		writel(reg_val, mdata->base + SPI_CFG1_REG);
355 	u32 reg_val;
362 	reg_val = readl(mdata->base + SPI_CMD_REG);
365 		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
367 			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
369 			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
373 		reg_val |= SPI_CMD_CPHA;
375 		reg_val &= ~SPI_CMD_CPHA;
377 		reg_val |= SPI_CMD_CPOL;
379 		reg_val &= ~SPI_CMD_CPOL;
383 		reg_val &= ~SPI_CMD_TXMSBF;
384 		reg_val &= ~SPI_CMD_RXMSBF;
386 		reg_val |= SPI_CMD_TXMSBF;
387 		reg_val |= SPI_CMD_RXMSBF;
392 	reg_val &= ~SPI_CMD_TX_ENDIAN;
393 	reg_val &= ~SPI_CMD_RX_ENDIAN;
395 	reg_val |= SPI_CMD_TX_ENDIAN;
396 	reg_val |= SPI_CMD_RX_ENDIAN;
402 			reg_val |= SPI_CMD_CS_POL;
404 			reg_val &= ~SPI_CMD_CS_POL;
407 			reg_val |= SPI_CMD_SAMPLE_SEL;
409 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
413 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
416 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
419 	reg_val &= ~SPI_CMD_DEASSERT;
421 	writel(reg_val, mdata->base + SPI_CMD_REG);
431 			reg_val = readl(mdata->base + SPI_CMD_REG);
432 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
433 			reg_val |= ((chip_config->tick_delay & 0x7)
435 			writel(reg_val, mdata->base + SPI_CMD_REG);
437 			reg_val = readl(mdata->base + SPI_CFG1_REG);
438 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
439 			reg_val |= ((chip_config->tick_delay & 0x7)
441 			writel(reg_val, mdata->base + SPI_CFG1_REG);
444 		reg_val = readl(mdata->base + SPI_CFG1_REG);
445 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
446 		reg_val |= ((chip_config->tick_delay & 0x3)
448 		writel(reg_val, mdata->base + SPI_CFG1_REG);
464 	u32 reg_val;
470 	reg_val = readl(mdata->base + SPI_CMD_REG);
472 		reg_val |= SPI_CMD_PAUSE_EN;
473 		writel(reg_val, mdata->base + SPI_CMD_REG);
475 		reg_val &= ~SPI_CMD_PAUSE_EN;
476 		writel(reg_val, mdata->base + SPI_CMD_REG);
485 	u32 div, sck_time, reg_val;
496 		reg_val = readl(mdata->base + SPI_CFG2_REG);
497 		reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
498 		reg_val |= (((sck_time - 1) & 0xffff)
500 		reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
501 		reg_val |= (((sck_time - 1) & 0xffff)
503 		writel(reg_val, mdata->base + SPI_CFG2_REG);
505 		reg_val = readl(mdata->base + SPI_CFG0_REG);
506 		reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
507 		reg_val |= (((sck_time - 1) & 0xff)
509 		reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
510 		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
511 		writel(reg_val, mdata->base + SPI_CFG0_REG);
517 	u32 packet_size, packet_loop, reg_val;
531 	reg_val = readl(mdata->base + SPI_CFG1_REG);
533 		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
535 		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
536 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
537 	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
538 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
539 	writel(reg_val, mdata->base + SPI_CFG1_REG);
629 	u32 reg_val;
643 			reg_val = 0;
644 			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
645 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);
704 	u32 reg_val = 0;
709 			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
711 				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
713 		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
748 	u32 cmd, reg_val, cnt, remainder, len;
753 	reg_val = readl(mdata->base + SPI_STATUS0_REG);
754 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
772 				reg_val = readl(mdata->base + SPI_RX_DATA_REG);
774 					&reg_val,
796 				reg_val = 0;
797 				memcpy(&reg_val,
800 				writel(reg_val, mdata->base + SPI_TX_DATA_REG);
946 	u32 reg_val, nio, tx_size;
957 	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
959 	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
960 	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
963 	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
965 		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
970 		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
973 		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
980 			reg_val |= SPI_CFG3_IPM_XMODE_EN;
982 			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
996 	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
997 	reg_val |= PIN_MODE_CFG(nio);
999 	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
1001 		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1003 		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1004 	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
1067 	reg_val = readl(mdata->base + SPI_CMD_REG);
1068 	reg_val |= SPI_CMD_TX_DMA;
1070 		reg_val |= SPI_CMD_RX_DMA;
1071 	writel(reg_val, mdata->base + SPI_CMD_REG);
1083 	reg_val = readl(mdata->base + SPI_CMD_REG);
1084 	reg_val &= ~SPI_CMD_TX_DMA;
1086 		reg_val &= ~SPI_CMD_RX_DMA;
1087 	writel(reg_val, mdata->base + SPI_CMD_REG);