drivers/spi/spi-microchip-core.c

21 #include <linux/spi/spi.h>
104 	u32 clk_gen; /* divider for spi output clock generated by the controller */
112 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)
114 	return readl(spi->regs + reg);
117 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val)
119 	writel(val, spi->regs + reg);
122 static inline void mchp_corespi_disable(struct mchp_corespi *spi)
124 	u32 control = mchp_corespi_read(spi, REG_CONTROL);
128 	mchp_corespi_write(spi, REG_CONTROL, control);
131 static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)
136 	fifo_max = min(spi->rx_len, FIFO_DEPTH);
138 	while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
139 		data = mchp_corespi_read(spi, REG_RX_DATA);
141 		if (spi->rx_buf)
142 			*spi->rx_buf++ = data;
145 	spi->rx_len -= i;
146 	spi->pending -= i;
149 static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
153 	mchp_corespi_disable(spi);
155 	control = mchp_corespi_read(spi, REG_CONTROL);
158 	mchp_corespi_write(spi, REG_CONTROL, control);
161 	mchp_corespi_write(spi, REG_CONTROL, control);
164 static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
168 	mchp_corespi_disable(spi);
170 	control = mchp_corespi_read(spi, REG_CONTROL);
172 	mchp_corespi_write(spi, REG_CONTROL, control);
175 	mchp_corespi_write(spi, REG_CONTROL, control);
178 static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)
187 	mchp_corespi_disable(spi);
197 	control = mchp_corespi_read(spi, REG_CONTROL);
200 	mchp_corespi_write(spi, REG_CONTROL, control);
203 	mchp_corespi_write(spi, REG_FRAMESUP, lenpart);
206 	mchp_corespi_write(spi, REG_CONTROL, control);
209 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)
214 	fifo_max = min(spi->tx_len, FIFO_DEPTH);
215 	mchp_corespi_set_xfer_size(spi, fifo_max);
217 	while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
218 		byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;
219 		mchp_corespi_write(spi, REG_TX_DATA, byte);
223 	spi->tx_len -= i;
224 	spi->pending += i;
227 static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
235 	mchp_corespi_disable(spi);
237 	mchp_corespi_write(spi, REG_FRAME_SIZE, bt);
239 	control = mchp_corespi_read(spi, REG_CONTROL);
241 	mchp_corespi_write(spi, REG_CONTROL, control);
244 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
247 	struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
250 	reg &= ~BIT(spi_get_chipselect(spi, 0));
251 	reg |= !disable << spi_get_chipselect(spi, 0);
256 static int mchp_corespi_setup(struct spi_device *spi)
258 	struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
266 	if (spi->mode & SPI_CS_HIGH) {
268 		reg |= BIT(spi_get_chipselect(spi, 0));
274 static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi)
277 	u32 control = mchp_corespi_read(spi, REG_CONTROL);
284 	mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
286 	/* max. possible spi clock rate is the apb clock rate */
287 	clk_hz = clk_get_rate(spi->clk);
298 	control = mchp_corespi_read(spi, REG_CONTROL);
301 	mchp_corespi_write(spi, REG_CONTROL, control);
303 	mchp_corespi_enable_ints(spi);
310 	mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT);
312 	control = mchp_corespi_read(spi, REG_CONTROL);
317 	mchp_corespi_write(spi, REG_CONTROL, control);
320 static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
324 	mchp_corespi_disable(spi);
326 	control = mchp_corespi_read(spi, REG_CONTROL);
327 	if (spi->clk_mode)
332 	mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);
333 	mchp_corespi_write(spi, REG_CONTROL, control);
334 	mchp_corespi_write(spi, REG_CONTROL, control | CONTROL_ENABLE);
337 static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)
360 	mchp_corespi_disable(spi);
362 	control = mchp_corespi_read(spi, REG_CONTROL);
366 	mchp_corespi_write(spi, REG_CONTROL, control);
369 	mchp_corespi_write(spi, REG_CONTROL, control);
375 	struct mchp_corespi *spi = spi_controller_get_devdata(host);
376 	u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;
384 		mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);
386 		if (spi->rx_len)
387 			mchp_corespi_read_fifo(spi);
389 		if (spi->tx_len)
390 			mchp_corespi_write_fifo(spi);
392 		if (!spi->rx_len)
397 		mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
400 		mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
404 			spi->rx_len, spi->tx_len);
408 		mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN);
412 			spi->rx_len, spi->tx_len);
421 static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi,
426 	clk_hz = clk_get_rate(spi->clk);
449 		spi->clk_mode = 0;
451 		spi->clk_mode = 1;
454 	spi->clk_gen = clk_gen;
462 	struct mchp_corespi *spi = spi_controller_get_devdata(host);
465 	ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);
471 	mchp_corespi_set_clk_gen(spi);
473 	spi->tx_buf = xfer->tx_buf;
474 	spi->rx_buf = xfer->rx_buf;
475 	spi->tx_len = xfer->len;
476 	spi->rx_len = xfer->len;
477 	spi->pending = 0;
479 	mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
480 				   ? FIFO_DEPTH : spi->tx_len);
482 	if (spi->tx_len)
483 		mchp_corespi_write_fifo(spi);
490 	struct spi_device *spi_dev = msg->spi;
491 	struct mchp_corespi *spi = spi_controller_get_devdata(host);
493 	mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
494 	mchp_corespi_set_mode(spi, spi_dev->mode);
502 	struct mchp_corespi *spi;
507 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
526 	spi = spi_controller_get_devdata(host);
528 	spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
529 	if (IS_ERR(spi->regs))
530 		return PTR_ERR(spi->regs);
532 	spi->irq = platform_get_irq(pdev, 0);
533 	if (spi->irq < 0)
534 		return spi->irq;
536 	ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
542 	spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
543 	if (IS_ERR(spi->clk))
544 		return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
547 	mchp_corespi_init(host, spi);
551 		mchp_corespi_disable(spi);
564 	struct mchp_corespi *spi = spi_controller_get_devdata(host);
566 	mchp_corespi_disable_ints(spi);
567 	mchp_corespi_disable(spi);
578 	{ .compatible = "microchip,mpfs-spi" },