Lines Matching defs:conf
180 u32 conf;
199 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
202 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
321 u32 conf;
352 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
353 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
355 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
356 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
357 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
363 u32 conf, conf_orig;
366 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
369 conf &= ~SPICC_BITLENGTH_MASK;
370 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
374 if (conf != conf_orig)
375 writel_relaxed(conf, spicc->base + SPICC_CONREG);
462 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
468 conf |= SPICC_ENABLE;
469 conf |= SPICC_MODE_MASTER;
475 conf |= SPICC_POL;
477 conf &= ~SPICC_POL;
490 conf |= SPICC_PHA;
492 conf &= ~SPICC_PHA;
497 conf |= SPICC_SSPOL;
499 conf &= ~SPICC_SSPOL;
502 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
504 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
507 conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));
510 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
512 writel_relaxed(conf, spicc->base + SPICC_CONREG);
525 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
533 writel_relaxed(conf, spicc->base + SPICC_CONREG);