drivers/spi/spi-ingenic.c

121 spi_ingenic_prepare_dma(struct spi_controller *ctlr, struct dma_chan *chan,
125 	struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
160 		desc->callback_param = ctlr;
174 static int spi_ingenic_dma_tx(struct spi_controller *ctlr,
179 	rx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_rx,
184 	tx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_tx,
187 		dmaengine_terminate_async(ctlr->dma_rx);
192 	dma_async_issue_pending(ctlr->dma_rx);
193 	dma_async_issue_pending(ctlr->dma_tx);
239 static int spi_ingenic_transfer_one(struct spi_controller *ctlr,
243 	struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
245 	bool can_dma = ctlr->can_dma && ctlr->can_dma(ctlr, spi, xfer);
249 	if (ctlr->cur_msg_mapped && can_dma)
250 		return spi_ingenic_dma_tx(ctlr, xfer, bits);
261 static int spi_ingenic_prepare_message(struct spi_controller *ctlr,
264 	struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
301 static int spi_ingenic_prepare_hardware(struct spi_controller *ctlr)
303 	struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
318 static int spi_ingenic_unprepare_hardware(struct spi_controller *ctlr)
320 	struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
329 static bool spi_ingenic_can_dma(struct spi_controller *ctlr,
336 	ret = dma_get_slave_caps(ctlr->dma_tx, &caps);
346 static int spi_ingenic_request_dma(struct spi_controller *ctlr,
354 	ctlr->dma_tx = chan;
359 	ctlr->dma_rx = chan;
361 	ctlr->can_dma = spi_ingenic_can_dma;
368 	struct spi_controller *ctlr = data;
370 	if (ctlr->dma_tx)
371 		dma_release_channel(ctlr->dma_tx);
372 	if (ctlr->dma_rx)
373 		dma_release_channel(ctlr->dma_rx);
387 	struct spi_controller *ctlr;
398 	ctlr = devm_spi_alloc_host(dev, sizeof(*priv));
399 	if (!ctlr) {
404 	priv = spi_controller_get_devdata(ctlr);
429 	platform_set_drvdata(pdev, ctlr);
431 	ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
432 	ctlr->unprepare_transfer_hardware = spi_ingenic_unprepare_hardware;
433 	ctlr->prepare_message = spi_ingenic_prepare_message;
434 	ctlr->set_cs = spi_ingenic_set_cs;
435 	ctlr->transfer_one = spi_ingenic_transfer_one;
436 	ctlr->mode_bits = SPI_MODE_3 | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH;
437 	ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
438 	ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
439 	ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
440 	ctlr->min_speed_hz = 7200;
441 	ctlr->max_speed_hz = pdata->max_speed_hz;
442 	ctlr->use_gpio_descriptors = true;
443 	ctlr->max_native_cs = pdata->max_native_cs;
444 	ctlr->num_chipselect = num_cs;
445 	ctlr->dev.of_node = pdev->dev.of_node;
447 	if (spi_ingenic_request_dma(ctlr, dev))
450 	ret = devm_add_action_or_reset(dev, spi_ingenic_release_dma, ctlr);
456 	ret = devm_spi_register_controller(dev, ctlr);