drivers/spi/spi-fsi.c

88 	int rc;
92 	rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
94 	if (rc)
95 		return rc;
108 	int rc;
112 	rc = fsi_device_read(ctx->bridge->fsi, FSI2SPI_STATUS, &sts_be,
114 	if (rc)
115 		return rc;
128 	int rc = 0;
139 	rc = mutex_lock_interruptible(&bridge->lock);
140 	if (rc)
141 		return rc;
144 	rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
146 	if (rc)
149 	rc = fsi_spi_check_status(ctx);
150 	if (rc)
153 	rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA0, &data_be,
155 	if (rc)
160 	rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA1, &data_be,
162 	if (rc)
170 	return rc;
175 	int rc = 0;
184 	rc = mutex_lock_interruptible(&bridge->lock);
185 	if (rc)
186 		return rc;
191 	rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA0, &data_be,
193 	if (rc)
197 	rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA1, &data_be,
199 	if (rc)
203 	rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
205 	if (rc)
208 	rc = fsi_spi_check_status(ctx);
212 	return rc;
243 	int rc;
247 	rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
249 	if (rc)
250 		return rc;
252 	rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
254 	if (rc)
255 		return rc;
262 	int rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, status);
264 	if (rc)
265 		return rc;
270 		rc = fsi_spi_reset(ctx);
271 		if (rc)
272 			return rc;
302 	int rc = 0;
316 			rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
317 			if (rc)
318 				return rc;
326 				rc = fsi_spi_status(ctx, &status, "TX");
327 				if (rc)
328 					return rc;
345 				rc = fsi_spi_status(ctx, &status, "RX");
346 				if (rc)
347 					return rc;
350 			rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
351 			if (rc)
352 				return rc;
365 	int rc;
380 		rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
381 		if (rc)
382 			return rc;
396 			rc = fsi_spi_reset(ctx);
397 			if (rc)
398 				return rc;
405 	rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
406 	if (rc)
407 		return rc;
409 	rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
410 	if (rc)
411 		return rc;
418 		rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
421 	return rc;
427 	int rc;
433 	rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev);
434 	if (rc)
443 			rc = -EINVAL;
449 		rc = fsi_spi_transfer_init(ctx);
450 		if (rc < 0)
473 					rc = -EINVAL;
489 		rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
490 		if (rc)
493 		rc = fsi_spi_transfer_data(ctx, transfer);
494 		if (rc)
498 			rc = fsi_spi_transfer_data(ctx, next);
499 			if (rc)
507 	mesg->status = rc;
510 	return rc;
520 	int rc;
526 	rc = fsi_spi_check_mux(fsi, dev);
527 	if (rc)
562 		rc = devm_spi_register_controller(dev, ctlr);
563 		if (rc)