drivers/spi/spi-armada-3700.c

128 	u32 val;
130 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
131 	val &= ~A3700_SPI_AUTO_CS;
132 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
137 	u32 val;
139 	val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
140 	val |= (A3700_SPI_EN << cs);
141 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
147 	u32 val;
149 	val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
150 	val &= ~(A3700_SPI_EN << cs);
151 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
157 	u32 val;
159 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
160 	val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
161 	val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
167 		val |= A3700_SPI_DATA_PIN0;
170 		val |= A3700_SPI_DATA_PIN1;
173 			val |= A3700_SPI_ADDR_PIN;
180 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
187 	u32 val;
189 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
191 		val |= A3700_SPI_FIFO_MODE;
193 		val &= ~A3700_SPI_FIFO_MODE;
194 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
200 	u32 val;
202 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
205 		val |= A3700_SPI_CLK_POL;
207 		val &= ~A3700_SPI_CLK_POL;
210 		val |= A3700_SPI_CLK_PHA;
212 		val &= ~A3700_SPI_CLK_PHA;
214 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
220 	u32 val;
232 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
233 	val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
235 	val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
236 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
239 		val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
240 		val |= A3700_SPI_CLK_CAPT_EDGE;
241 		spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
247 	u32 val;
249 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
251 		val |= A3700_SPI_BYTE_LEN;
253 		val &= ~A3700_SPI_BYTE_LEN;
254 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
262 	u32 val;
264 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
265 	val |= A3700_SPI_FIFO_FLUSH;
266 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
269 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
270 		if (!(val & A3700_SPI_FIFO_FLUSH))
281 	u32 val;
285 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
286 	val |= A3700_SPI_SRST;
287 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
291 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
292 	val &= ~A3700_SPI_SRST;
293 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
404 	u32 val;
406 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
407 	val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
408 	val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
409 	val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
410 	val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
411 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
447 	u32 val = 0;
467 			val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
469 			spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
475 			val = 0;
477 				val = (val << 8) | a3700_spi->tx_buf[0];
480 			spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
487 	u32 val;
489 	val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
490 	return (val & A3700_SPI_WFIFO_FULL);
495 	u32 val;
498 		val = *(u32 *)a3700_spi->tx_buf;
499 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));
509 	u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
511 	return (val & A3700_SPI_RFIFO_EMPTY);
516 	u32 val;
519 		val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
521 			val = le32_to_cpu(val);
522 			memcpy(a3700_spi->rx_buf, &val, 4);
533 				*a3700_spi->rx_buf = val & 0xff;
534 				val >>= 8;
548 	u32 val;
550 	val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
551 	val |= A3700_SPI_XFER_STOP;
552 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
555 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
556 		if (!(val & A3700_SPI_XFER_START))
563 	val &= ~A3700_SPI_XFER_STOP;
564 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
597 	u32 val;
629 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
630 		val &= ~A3700_SPI_RW_EN;
631 		val |= A3700_SPI_XFER_START;
632 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
635 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
636 		val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
637 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
709 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
710 		val |= A3700_SPI_XFER_STOP;
711 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
715 		val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
716 		if (!(val & A3700_SPI_XFER_START))
727 	val &= ~A3700_SPI_XFER_STOP;
728 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
744 	u32 val;
758 			val = *a3700_spi->tx_buf;
760 			val = *(u32 *)a3700_spi->tx_buf;
762 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
769 		val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
771 		memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);