Lines Matching refs:ctrl
209 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
281 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
284 struct regmap *wcd_regmap = ctrl->regmap;
301 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
304 struct regmap *wcd_regmap = ctrl->regmap;
321 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
324 *val = readl(ctrl->mmio + reg);
328 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
331 writel(val, ctrl->mmio + reg);
353 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
360 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
372 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
379 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
386 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
391 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
397 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
398 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
405 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
411 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
417 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
431 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
444 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
448 if (swrm_wait_for_wr_fifo_avail(ctrl))
452 reinit_completion(&ctrl->broadcast);
455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
457 if (ctrl->version <= SWRM_VERSION_1_3_0)
461 swrm_wait_for_wr_fifo_done(ctrl);
466 ret = wait_for_completion_timeout(&ctrl->broadcast,
479 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
485 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
491 swrm_wait_for_wr_fifo_avail(ctrl);
495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
499 if (swrm_wait_for_rd_fifo_avail(ctrl))
503 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
508 if (cmd_id != ctrl->rcmd_id) {
512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
514 ctrl->reg_write(ctrl,
515 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
527 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
532 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
537 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
543 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
551 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
556 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
557 ctrl->slave_status = val;
564 ctrl->status[i] = s;
571 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
574 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
589 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
600 if (!ctrl->status[i])
604 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
607 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
618 ctrl->clock_stop_not_supported = false;
624 ctrl->clock_stop_not_supported = true;
637 complete(&ctrl->enumeration);
643 struct qcom_swrm_ctrl *ctrl = dev_id;
646 ret = pm_runtime_get_sync(ctrl->dev);
648 dev_err_ratelimited(ctrl->dev,
651 pm_runtime_put_noidle(ctrl->dev);
655 if (ctrl->wake_irq > 0) {
656 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
657 disable_irq_nosync(ctrl->wake_irq);
660 pm_runtime_mark_last_busy(ctrl->dev);
661 pm_runtime_put_autosuspend(ctrl->dev);
668 struct qcom_swrm_ctrl *ctrl = dev_id;
673 clk_prepare_enable(ctrl->hclk);
675 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
677 intr_sts_masked = intr_sts & ctrl->intr_mask;
687 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
689 dev_err_ratelimited(ctrl->dev,
692 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
698 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
699 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
700 if (ctrl->slave_status == slave_status) {
701 dev_dbg(ctrl->dev, "Slave status not changed %x\n",
704 qcom_swrm_get_device_status(ctrl);
705 qcom_swrm_enumerate(&ctrl->bus);
706 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
710 dev_err_ratelimited(ctrl->dev,
713 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
714 ctrl->reg_write(ctrl,
715 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
716 ctrl->intr_mask);
719 ctrl->reg_read(ctrl,
720 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
722 dev_err_ratelimited(ctrl->dev,
727 ctrl->reg_read(ctrl,
728 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
730 dev_err_ratelimited(ctrl->dev,
735 ctrl->reg_read(ctrl,
736 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
738 dev_err(ctrl->dev,
741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
744 ctrl->reg_read(ctrl,
745 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
747 dev_err_ratelimited(ctrl->dev,
750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
753 dev_err_ratelimited(ctrl->dev,
756 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
757 ctrl->reg_write(ctrl,
758 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
759 ctrl->intr_mask);
762 dev_err_ratelimited(ctrl->dev,
765 ctrl->intr_mask &=
767 ctrl->reg_write(ctrl,
768 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
769 ctrl->intr_mask);
772 complete(&ctrl->broadcast);
781 ctrl->reg_read(ctrl,
782 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
784 dev_err(ctrl->dev,
792 dev_err_ratelimited(ctrl->dev,
799 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
801 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
803 intr_sts_masked = intr_sts & ctrl->intr_mask;
806 clk_disable_unprepare(ctrl->hclk);
810 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
816 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
824 dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
830 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
835 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
836 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
838 reset_control_reset(ctrl->audio_cgcr);
840 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
843 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
845 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
847 if (ctrl->version < SWRM_VERSION_2_0_0)
848 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
852 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
854 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
856 if (ctrl->version == SWRM_VERSION_1_7_0) {
857 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
858 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
860 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
861 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
862 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
865 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
869 if (ctrl->version >= SWRM_VERSION_1_5_1) {
870 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
874 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
879 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
882 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
885 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
889 if (ctrl->mmio) {
890 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
895 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
899 swrm_wait_for_frame_gen_enabled(ctrl);
900 ctrl->slave_status = 0;
901 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
902 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
903 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
910 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
912 if (ctrl->version >= SWRM_VERSION_2_0_0) {
923 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
933 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
943 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
957 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
960 ctrl->reg_read(ctrl, reg, &val);
962 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
963 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
965 return ctrl->reg_write(ctrl, reg, val);
972 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
974 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
983 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
989 pcfg = &ctrl->pconfig[params->port_num];
995 ret = ctrl->reg_write(ctrl, reg, value);
1002 ret = ctrl->reg_write(ctrl, reg, value);
1010 ret = ctrl->reg_write(ctrl, reg, value);
1018 ret = ctrl->reg_write(ctrl, reg, value);
1027 ret = ctrl->reg_write(ctrl, reg, value);
1031 ret = ctrl->reg_write(ctrl, reg, value);
1039 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1051 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1054 ctrl->reg_read(ctrl, reg, &val);
1061 return ctrl->reg_write(ctrl, reg, val);
1078 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1089 pcfg = &ctrl->pconfig[p_rt->num];
1106 pcfg = &ctrl->pconfig[m_port];
1108 pcfg = &ctrl->pconfig[i];
1139 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1146 mutex_lock(&ctrl->port_lock);
1150 port_mask = &ctrl->dout_port_mask;
1152 port_mask = &ctrl->din_port_mask;
1158 mutex_unlock(&ctrl->port_lock);
1161 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1187 mutex_lock(&ctrl->port_lock);
1195 if (ctrl->bus.id != m_rt->bus->id)
1199 maxport = ctrl->num_dout_ports;
1200 port_mask = &ctrl->dout_port_mask;
1202 maxport = ctrl->num_din_ports;
1203 port_mask = &ctrl->din_port_mask;
1217 dev_err(ctrl->dev, "All ports busy\n");
1229 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1232 mutex_unlock(&ctrl->port_lock);
1241 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1242 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1245 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1248 qcom_swrm_stream_free_ports(ctrl, sruntime);
1256 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1257 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1259 qcom_swrm_stream_free_ports(ctrl, sruntime);
1260 sdw_stream_remove_master(&ctrl->bus, sruntime);
1268 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1270 ctrl->sruntime[dai->id] = stream;
1277 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1279 return ctrl->sruntime[dai->id];
1285 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1288 ret = pm_runtime_get_sync(ctrl->dev);
1290 dev_err_ratelimited(ctrl->dev,
1293 pm_runtime_put_noidle(ctrl->dev);
1303 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1305 swrm_wait_for_wr_fifo_done(ctrl);
1306 pm_runtime_mark_last_busy(ctrl->dev);
1307 pm_runtime_put_autosuspend(ctrl->dev);
1324 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1326 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1329 struct device *dev = ctrl->dev;
1342 if (i < ctrl->num_dout_ports)
1356 return devm_snd_soc_register_component(ctrl->dev,
1361 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1363 struct device_node *np = ctrl->dev->of_node;
1376 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1378 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1379 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1385 if (val > ctrl->num_din_ports)
1388 ctrl->num_din_ports = val;
1394 if (val > ctrl->num_dout_ports)
1397 ctrl->num_dout_ports = val;
1399 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1404 set_bit(0, &ctrl->dout_port_mask);
1405 set_bit(0, &ctrl->din_port_mask);
1430 if (ctrl->version <= SWRM_VERSION_1_3_0)
1454 ctrl->pconfig[i + 1].si = si[i];
1456 ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1457 ctrl->pconfig[i + 1].off1 = off1[i];
1458 ctrl->pconfig[i + 1].off2 = off2[i];
1459 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1460 ctrl->pconfig[i + 1].hstart = hstart[i];
1461 ctrl->pconfig[i + 1].hstop = hstop[i];
1462 ctrl->pconfig[i + 1].word_length = word_length[i];
1463 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1464 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1473 struct qcom_swrm_ctrl *ctrl = s_file->private;
1476 ret = pm_runtime_get_sync(ctrl->dev);
1478 dev_err_ratelimited(ctrl->dev,
1481 pm_runtime_put_noidle(ctrl->dev);
1485 for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1486 ctrl->reg_read(ctrl, reg, ®_val);
1489 pm_runtime_mark_last_busy(ctrl->dev);
1490 pm_runtime_put_autosuspend(ctrl->dev);
1503 struct qcom_swrm_ctrl *ctrl;
1508 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1509 if (!ctrl)
1513 ctrl->max_reg = data->max_reg;
1514 ctrl->reg_layout = data->reg_layout;
1515 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1516 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1522 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1523 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1524 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1525 if (!ctrl->regmap)
1528 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1529 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1530 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1531 if (IS_ERR(ctrl->mmio))
1532 return PTR_ERR(ctrl->mmio);
1536 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1537 if (IS_ERR(ctrl->audio_cgcr)) {
1538 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1539 ret = PTR_ERR(ctrl->audio_cgcr);
1544 ctrl->irq = of_irq_get(dev->of_node, 0);
1545 if (ctrl->irq < 0) {
1546 ret = ctrl->irq;
1550 ctrl->hclk = devm_clk_get(dev, "iface");
1551 if (IS_ERR(ctrl->hclk)) {
1552 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1556 clk_prepare_enable(ctrl->hclk);
1558 ctrl->dev = dev;
1559 dev_set_drvdata(&pdev->dev, ctrl);
1560 mutex_init(&ctrl->port_lock);
1561 init_completion(&ctrl->broadcast);
1562 init_completion(&ctrl->enumeration);
1564 ctrl->bus.ops = &qcom_swrm_ops;
1565 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1566 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1567 ctrl->bus.clk_stop_timeout = 300;
1569 ret = qcom_swrm_get_port_config(ctrl);
1573 params = &ctrl->bus.params;
1578 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1582 prop = &ctrl->bus.prop;
1590 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1592 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1596 "soundwire", ctrl);
1602 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1603 if (ctrl->wake_irq > 0) {
1604 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1607 "swr_wake_irq", ctrl);
1614 ctrl->bus.controller_id = -1;
1616 if (ctrl->version > SWRM_VERSION_1_3_0) {
1617 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1618 ctrl->bus.controller_id = val;
1621 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1628 qcom_swrm_init(ctrl);
1629 wait_for_completion_timeout(&ctrl->enumeration,
1631 ret = qcom_swrm_register_dais(ctrl);
1636 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1637 ctrl->version & 0xffff);
1646 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1647 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1654 sdw_bus_master_delete(&ctrl->bus);
1656 clk_disable_unprepare(ctrl->hclk);
1663 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1665 sdw_bus_master_delete(&ctrl->bus);
1666 clk_disable_unprepare(ctrl->hclk);
1671 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1674 if (ctrl->wake_irq > 0) {
1675 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1676 disable_irq_nosync(ctrl->wake_irq);
1679 clk_prepare_enable(ctrl->hclk);
1681 if (ctrl->clock_stop_not_supported) {
1682 reinit_completion(&ctrl->enumeration);
1683 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1686 qcom_swrm_init(ctrl);
1689 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1690 dev_err(ctrl->dev, "link failed to connect\n");
1693 wait_for_completion_timeout(&ctrl->enumeration,
1695 qcom_swrm_get_device_status(ctrl);
1696 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1698 reset_control_reset(ctrl->audio_cgcr);
1700 if (ctrl->version == SWRM_VERSION_1_7_0) {
1701 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1702 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1704 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1705 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1706 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1709 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1711 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1714 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1715 if (ctrl->version < SWRM_VERSION_2_0_0)
1716 ctrl->reg_write(ctrl,
1717 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1718 ctrl->intr_mask);
1719 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1720 ctrl->intr_mask);
1723 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1724 dev_err(ctrl->dev, "link failed to connect\n");
1726 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1728 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1736 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1739 swrm_wait_for_wr_fifo_done(ctrl);
1740 if (!ctrl->clock_stop_not_supported) {
1742 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1743 if (ctrl->version < SWRM_VERSION_2_0_0)
1744 ctrl->reg_write(ctrl,
1745 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1746 ctrl->intr_mask);
1747 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1748 ctrl->intr_mask);
1750 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1756 ret = sdw_bus_clk_stop(&ctrl->bus);
1763 clk_disable_unprepare(ctrl->hclk);
1767 if (ctrl->wake_irq > 0) {
1768 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1769 enable_irq(ctrl->wake_irq);