soc/qcom/spm.c

256 static inline void spm_register_write(struct spm_driver_data *drv,
259 	if (drv->reg_data->reg_offset[reg])
260 		writel_relaxed(val, drv->reg_base +
261 				drv->reg_data->reg_offset[reg]);
265 static inline void spm_register_write_sync(struct spm_driver_data *drv,
270 	if (!drv->reg_data->reg_offset[reg])
274 		writel_relaxed(val, drv->reg_base +
275 				drv->reg_data->reg_offset[reg]);
276 		ret = readl_relaxed(drv->reg_base +
277 				drv->reg_data->reg_offset[reg]);
284 static inline u32 spm_register_read(struct spm_driver_data *drv,
287 	return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
290 void spm_set_low_power_mode(struct spm_driver_data *drv,
296 	start_index = drv->reg_data->start_index[mode];
298 	ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
302 	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
307 	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
309 	drv->volt_sel = selector;
312 	return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
317 	struct spm_driver_data *drv = rdev_get_drvdata(rdev);
319 	return drv->volt_sel;
331 	struct spm_driver_data *drv = data;
336 	volt_sel = drv->volt_sel;
339 	avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
340 	vctl = spm_register_read(drv, SPM_REG_VCTL);
341 	data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
342 	data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
349 		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
353 	spm_register_write(drv, SPM_REG_RST, 1);
360 	spm_register_write(drv, SPM_REG_VCTL, vctl);
361 	spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
362 	spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
367 				     drv, SPM_REG_STS1)) {
368 		dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
378 		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
384 		spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
414 static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
418 		.driver_data = drv,
425 	if (!drv->reg_data->set_vdd)
438 	rdesc->linear_ranges = drv->reg_data->range;
441 	rdesc->ramp_delay = drv->reg_data->ramp_delay;
447 	drv->reg_cpu = ret;
448 	dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
454 	drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
456 	ret = linear_range_get_selector_high(drv->reg_data->range,
457 					     drv->reg_data->init_uV,
458 					     &drv->volt_sel,
466 	smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
511 	struct spm_driver_data *drv;
514 	drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
515 	if (!drv)
518 	drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
519 	if (IS_ERR(drv->reg_base))
520 		return PTR_ERR(drv->reg_base);
526 	drv->reg_data = match_id->data;
527 	drv->dev = &pdev->dev;
528 	platform_set_drvdata(pdev, drv);
531 	addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
532 	__iowrite32_copy(addr, drv->reg_data->seq,
533 			ARRAY_SIZE(drv->reg_data->seq) / 4);
541 	spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
542 	spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
543 	spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
544 	spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
545 	spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
546 	spm_register_write(drv, SPM_REG_PMIC_DATA_0,
547 				drv->reg_data->pmic_data[0]);
548 	spm_register_write(drv, SPM_REG_PMIC_DATA_1,
549 				drv->reg_data->pmic_data[1]);
552 	if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
553 		spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
556 		return spm_register_regulator(&pdev->dev, drv);