Lines Matching defs:mc
351 * and including 'mc' fits within a cacheline (yay!). The 'config' part
359 struct qm_mc mc;
857 struct qm_mc *mc = &portal->mc;
859 mc->cr = portal->addr.ce + QM_CL_CR;
860 mc->rr = portal->addr.ce + QM_CL_RR0;
868 rr0 = mc->rr->verb;
869 rr1 = (mc->rr+1)->verb;
871 mc->rridx = 1;
873 mc->rridx = 0;
874 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
876 mc->state = qman_mc_idle;
884 struct qm_mc *mc = &portal->mc;
886 DPAA_ASSERT(mc->state == qman_mc_idle);
887 if (mc->state != qman_mc_idle)
894 struct qm_mc *mc = &portal->mc;
896 DPAA_ASSERT(mc->state == qman_mc_idle);
898 mc->state = qman_mc_user;
900 dpaa_zero(mc->cr);
901 return mc->cr;
906 struct qm_mc *mc = &portal->mc;
907 union qm_mc_result *rr = mc->rr + mc->rridx;
909 DPAA_ASSERT(mc->state == qman_mc_user);
911 mc->cr->_ncw_verb = myverb | mc->vbit;
912 dpaa_flush(mc->cr);
915 mc->state = qman_mc_hw;
921 struct qm_mc *mc = &portal->mc;
922 union qm_mc_result *rr = mc->rr + mc->rridx;
924 DPAA_ASSERT(mc->state == qman_mc_hw);
934 mc->rridx ^= 1;
935 mc->vbit ^= QM_MCC_VERB_VBIT;
937 mc->state = qman_mc_idle;