Lines Matching refs:reg
59 static inline u32 cbc_readl(int reg)
61 int offset = cpubiuctrl_regs[reg];
64 (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
70 static inline void cbc_writel(u32 val, int reg)
72 int offset = cpubiuctrl_regs[reg];
75 (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
209 u32 reg;
211 reg = brcmstb_get_family_id();
214 if (BRCM_ID(reg) == a72_b53_mach_compat[i])
222 reg = cbc_readl(CPU_CREDIT_REG);
224 reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
226 reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
228 reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
229 reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
231 cbc_writel(reg, CPU_CREDIT_REG);
234 reg = cbc_readl(CPU_MCP_FLOW_REG);
236 reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
238 cbc_writel(reg, CPU_MCP_FLOW_REG);
243 reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
244 reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
245 reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
246 reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
248 reg |= 8;
249 reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
250 cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);