sh/clk/cpg.c

11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk)
21 	if (clk->flags & CLK_ENABLE_REG_8BIT)
22 		return ioread8(clk->mapped_reg);
23 	else if (clk->flags & CLK_ENABLE_REG_16BIT)
24 		return ioread16(clk->mapped_reg);
26 	return ioread32(clk->mapped_reg);
29 static void sh_clk_write(int value, struct clk *clk)
31 	if (clk->flags & CLK_ENABLE_REG_8BIT)
32 		iowrite8(value, clk->mapped_reg);
33 	else if (clk->flags & CLK_ENABLE_REG_16BIT)
34 		iowrite16(value, clk->mapped_reg);
36 		iowrite32(value, clk->mapped_reg);
39 static int sh_clk_mstp_enable(struct clk *clk)
41 	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
42 	if (clk->status_reg) {
45 		void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
46 			(phys_addr_t)clk->enable_reg + clk->mapped_reg;
48 		if (clk->flags & CLK_ENABLE_REG_8BIT)
50 		else if (clk->flags & CLK_ENABLE_REG_16BIT)
56 		     (read(mapped_status) & (1 << clk->enable_bit)) && i;
61 			       clk->enable_reg, clk->enable_bit);
68 static void sh_clk_mstp_disable(struct clk *clk)
70 	sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);
79 int __init sh_clk_mstp_register(struct clk *clks, int nr)
81 	struct clk *clkp;
97 static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
99 	return clk->priv;
102 static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
104 	return clk_to_div_table(clk)->div_mult_table;
110 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
112 	return clk_rate_table_round(clk, clk->freq_table, rate);
115 static unsigned long sh_clk_div_recalc(struct clk *clk)
117 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
120 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
121 			     table, clk->arch_flags ? &clk->arch_flags : NULL);
123 	idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
125 	return clk->freq_table[idx].frequency;
128 static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
130 	struct clk_div_table *dt = clk_to_div_table(clk);
134 	idx = clk_rate_table_find(clk, clk->freq_table, rate);
138 	value = sh_clk_read(clk);
139 	value &= ~(clk->div_mask << clk->enable_bit);
140 	value |= (idx << clk->enable_bit);
141 	sh_clk_write(value, clk);
145 		dt->kick(clk);
150 static int sh_clk_div_enable(struct clk *clk)
152 	if (clk->div_mask == SH_CLK_DIV6_MSK) {
153 		int ret = sh_clk_div_set_rate(clk, clk->rate);
158 	sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
162 static void sh_clk_div_disable(struct clk *clk)
166 	val = sh_clk_read(clk);
174 	if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
175 		val |= clk->div_mask;
177 	sh_clk_write(val, clk);
194 static int __init sh_clk_init_parent(struct clk *clk)
198 	if (clk->parent)
201 	if (!clk->parent_table || !clk->parent_num)
204 	if (!clk->src_width) {
209 	val  = (sh_clk_read(clk) >> clk->src_shift);
210 	val &= (1 << clk->src_width) - 1;
212 	if (val >= clk->parent_num) {
217 	clk_reparent(clk, clk->parent_table[val]);
218 	if (!clk->parent) {
226 static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
229 	struct clk *clkp;
279 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
281 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
285 	if (!clk->parent_table || !clk->parent_num)
289 	for (i = 0; i < clk->parent_num; i++)
290 		if (clk->parent_table[i] == parent)
293 	if (i == clk->parent_num)
296 	ret = clk_reparent(clk, parent);
300 	value = sh_clk_read(clk) &
301 		~(((1 << clk->src_width) - 1) << clk->src_shift);
303 	sh_clk_write(value | (i << clk->src_shift), clk);
306 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
321 int __init sh_clk_div6_register(struct clk *clks, int nr)
327 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
336 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
338 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
348 		value = sh_clk_read(clk) & ~(1 << 7);
350 		value = sh_clk_read(clk) | (1 << 7);
352 	ret = clk_reparent(clk, parent);
356 	sh_clk_write(value, clk);
359 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
360 			     table, &clk->arch_flags);
374 int __init sh_clk_div4_register(struct clk *clks, int nr,
380 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
387 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
395 static unsigned long fsidiv_recalc(struct clk *clk)
399 	value = __raw_readl(clk->mapping->base);
403 		return clk->parent->rate;
405 	return clk->parent->rate / value;
408 static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
410 	return clk_rate_div_range_round(clk, 1, 0xffff, rate);
413 static void fsidiv_disable(struct clk *clk)
415 	__raw_writel(0, clk->mapping->base);
418 static int fsidiv_enable(struct clk *clk)
422 	value  = __raw_readl(clk->mapping->base) >> 16;
426 	__raw_writel((value << 16) | 0x3, clk->mapping->base);
431 static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
435 	idx = (clk->parent->rate / rate) & 0xffff;
437 		__raw_writel(0, clk->mapping->base);
439 		__raw_writel(idx << 16, clk->mapping->base);
452 int __init sh_clk_fsidiv_register(struct clk *clks, int nr)