Lines Matching defs:ha
15 uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr)
17 return readl((void __iomem *)(ha->nx_pcibase + addr));
20 void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val)
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr));
25 static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr)
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr);
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num));
33 ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n",
41 int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
46 ret_val = qla4_83xx_set_win_base(ha, addr);
49 *data = qla4_83xx_rd_reg(ha, QLA83XX_WILDCARD);
52 ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n",
59 int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
64 ret_val = qla4_83xx_set_win_base(ha, addr);
67 qla4_83xx_wr_reg(ha, QLA83XX_WILDCARD, data);
69 ql4_printk(KERN_ERR, ha, "%s: failed wrt to addr 0x%x, data 0x%x\n",
75 static int qla4_83xx_flash_lock(struct scsi_qla_host *ha)
83 lock_status = qla4_83xx_rd_reg(ha, QLA83XX_FLASH_LOCK);
88 lock_owner = qla4_83xx_rd_reg(ha,
90 ql4_printk(KERN_ERR, ha, "%s: flash lock by func %d failed, held by func %d\n",
91 __func__, ha->func_num, lock_owner);
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num);
102 static void qla4_83xx_flash_unlock(struct scsi_qla_host *ha)
105 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, 0xFF);
106 qla4_83xx_rd_reg(ha, QLA83XX_FLASH_UNLOCK);
109 int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr,
117 ret_val = qla4_83xx_flash_lock(ha);
122 ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
129 ret_val = qla4_83xx_wr_reg_indirect(ha,
133 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW\n!",
138 ret_val = qla4_83xx_rd_reg_indirect(ha,
142 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
153 qla4_83xx_flash_unlock(ha);
159 int qla4_83xx_lockless_flash_read_u32(struct scsi_qla_host *ha,
172 ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
178 ret_val = qla4_83xx_wr_reg_indirect(ha, QLA83XX_FLASH_DIRECT_WINDOW,
181 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
192 ret_val = qla4_83xx_rd_reg_indirect(ha,
196 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
208 ret_val = qla4_83xx_wr_reg_indirect(ha,
212 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
222 ret_val = qla4_83xx_rd_reg_indirect(ha,
226 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
241 void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
243 if (qla4_83xx_flash_lock(ha))
244 ql4_printk(KERN_INFO, ha, "%s: Resetting rom lock\n", __func__);
250 qla4_83xx_flash_unlock(ha);
256 static int qla4_83xx_lock_recovery(struct scsi_qla_host *ha)
262 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
269 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
270 (ha->func_num << 2) | INTENT_TO_RECOVER);
275 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
276 if ((lockid & 0x3C) != (ha->func_num << 2))
279 ql4_printk(KERN_INFO, ha, "%s: IDC Lock recovery initiated for func %d\n",
280 __func__, ha->func_num);
283 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
284 (ha->func_num << 2) | PROCEED_TO_RECOVER);
287 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, 0xFF);
288 ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_UNLOCK);
291 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, 0);
294 lock = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK);
296 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK_ID);
297 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->func_num;
298 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, lockid);
308 int qla4_83xx_drv_lock(struct scsi_qla_host *ha)
320 status = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK);
324 lock_id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
325 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->func_num;
326 qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, lock_id);
333 first_owner = ha->isp_ops->rd_reg_direct(ha,
338 tmo_owner = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
341 ql4_printk(KERN_INFO, ha, "%s: Lock by func %d failed after 2s, lock held by func %d, lock count %d, first_owner %d\n",
342 __func__, ha->func_num, func_num, lock_cnt,
350 ql4_printk(KERN_INFO, ha, "%s: IDC lock failed for func %d\n",
351 __func__, ha->func_num);
356 ret_val = qla4_83xx_lock_recovery(ha);
359 ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d successful\n",
360 __func__, ha->func_num);
365 ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d failed, Retrying timeout\n",
366 __func__, ha->func_num);
376 void qla4_83xx_drv_unlock(struct scsi_qla_host *ha)
380 id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
382 if ((id & 0xFF) != ha->func_num) {
383 ql4_printk(KERN_ERR, ha, "%s: IDC Unlock by %d failed, lock owner is %d\n",
384 __func__, ha->func_num, (id & 0xFF));
388 /* Keep lock counter value, update the ha->func_num to 0xFF */
389 qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, (id | 0xFF));
390 qla4_83xx_rd_reg(ha, QLA83XX_DRV_UNLOCK);
393 void qla4_83xx_set_idc_dontreset(struct scsi_qla_host *ha)
397 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
399 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
400 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
404 void qla4_83xx_clear_idc_dontreset(struct scsi_qla_host *ha)
408 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
410 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
411 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
415 int qla4_83xx_idc_dontreset(struct scsi_qla_host *ha)
419 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
438 int qla4_83xx_can_perform_reset(struct scsi_qla_host *ha)
452 dev_part1 = qla4_83xx_rd_reg(ha,
453 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]);
454 dev_part2 = qla4_83xx_rd_reg(ha, QLA83XX_CRB_DEV_PART_INFO2);
455 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]);
492 if (!nic_present && (ha->func_num == iscsi_func_low)) {
493 DEBUG2(ql4_printk(KERN_INFO, ha,
495 __func__, ha->func_num));
504 * @ha: pointer to adapter structure
508 void qla4_83xx_need_reset_handler(struct scsi_qla_host *ha)
513 ql4_printk(KERN_INFO, ha, "%s: Performing ISP error recovery\n",
516 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
517 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: reset acknowledged\n",
519 qla4_8xxx_set_rst_ready(ha);
523 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
527 ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n",
532 ha->isp_ops->idc_unlock(ha);
534 ha->isp_ops->idc_lock(ha);
536 dev_state = qla4_8xxx_rd_direct(ha,
540 qla4_8xxx_set_rst_ready(ha);
541 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
542 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
543 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
545 ql4_printk(KERN_INFO, ha, "%s: drv_state = 0x%x, drv_active = 0x%x\n",
550 ql4_printk(KERN_INFO, ha, "%s: %s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
556 ha->isp_ops->idc_unlock(ha);
558 ha->isp_ops->idc_lock(ha);
560 drv_state = qla4_8xxx_rd_direct(ha,
562 drv_active = qla4_8xxx_rd_direct(ha,
567 ql4_printk(KERN_INFO, ha, "%s: Reset_owner turning off drv_active of non-acking function 0x%x\n",
570 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE,
574 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
576 qla4_8xxx_device_bootstrap(ha);
580 void qla4_83xx_get_idc_param(struct scsi_qla_host *ha)
584 ret_val = qla4_83xx_flash_read_u32(ha, QLA83XX_IDC_PARAM_ADDR,
587 ha->nx_dev_init_timeout = idc_params & 0xFFFF;
588 ha->nx_reset_timeout = (idc_params >> 16) & 0xFFFF;
590 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
591 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
594 DEBUG2(ql4_printk(KERN_DEBUG, ha,
595 "%s: ha->nx_dev_init_timeout = %d, ha->nx_reset_timeout = %d\n",
596 __func__, ha->nx_dev_init_timeout,
597 ha->nx_reset_timeout));
602 static void qla4_83xx_dump_reset_seq_hdr(struct scsi_qla_host *ha)
606 if (!ha->reset_tmplt.buff) {
607 ql4_printk(KERN_ERR, ha, "%s: Error: Invalid reset_seq_template\n",
612 phdr = ha->reset_tmplt.buff;
614 DEBUG2(ql4_printk(KERN_INFO, ha,
622 static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha)
630 dest = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_ADDR);
631 size = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_SIZE);
642 ql4_printk(KERN_ERR, ha, "%s: Failed to allocate memory for boot loader cache\n",
648 ret_val = qla4_83xx_lockless_flash_read_u32(ha, src, p_cache,
651 ql4_printk(KERN_ERR, ha, "%s: Error reading firmware from flash\n",
655 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Read firmware from flash\n",
659 ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,
662 ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n",
667 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Wrote firmware size %d to MS\n",
677 static int qla4_83xx_check_cmd_peg_status(struct scsi_qla_host *ha)
683 val = qla4_83xx_rd_reg(ha, QLA83XX_CMDPEG_STATE);
685 DEBUG2(ql4_printk(KERN_INFO, ha,
701 * @ha : Pointer to adapter structure
707 static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr,
715 ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
723 ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
736 ha->reset_tmplt.seq_error++;
737 ql4_printk(KERN_ERR, ha, "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
744 static int qla4_83xx_reset_seq_checksum_test(struct scsi_qla_host *ha)
747 uint16_t *buff = (uint16_t *)ha->reset_tmplt.buff;
748 int u16_count = ha->reset_tmplt.hdr->size / sizeof(uint16_t);
761 ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n",
771 * @ha: Pointer to adapter structure
773 void qla4_83xx_read_reset_template(struct scsi_qla_host *ha)
779 ha->reset_tmplt.seq_error = 0;
780 ha->reset_tmplt.buff = vmalloc(QLA83XX_RESTART_TEMPLATE_SIZE);
781 if (ha->reset_tmplt.buff == NULL) {
782 ql4_printk(KERN_ERR, ha, "%s: Failed to allocate reset template resources\n",
787 p_buff = ha->reset_tmplt.buff;
793 DEBUG2(ql4_printk(KERN_INFO, ha,
798 ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
801 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
806 ha->reset_tmplt.hdr =
807 (struct qla4_83xx_reset_template_hdr *)ha->reset_tmplt.buff;
810 tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
812 (ha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
813 ql4_printk(KERN_ERR, ha, "%s: Template Header size %d is invalid, tmplt_hdr_def_size %d\n",
818 addr = QLA83XX_RESET_TEMPLATE_ADDR + ha->reset_tmplt.hdr->hdr_size;
819 p_buff = ha->reset_tmplt.buff + ha->reset_tmplt.hdr->hdr_size;
820 tmplt_hdr_def_size = (ha->reset_tmplt.hdr->size -
821 ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t);
823 DEBUG2(ql4_printk(KERN_INFO, ha,
825 __func__, ha->reset_tmplt.hdr->size));
828 ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
831 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
837 if (qla4_83xx_reset_seq_checksum_test(ha)) {
838 ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n",
842 DEBUG2(ql4_printk(KERN_INFO, ha,
847 ha->reset_tmplt.init_offset = ha->reset_tmplt.buff +
848 ha->reset_tmplt.hdr->init_seq_offset;
849 ha->reset_tmplt.start_offset = ha->reset_tmplt.buff +
850 ha->reset_tmplt.hdr->start_seq_offset;
851 ha->reset_tmplt.stop_offset = ha->reset_tmplt.buff +
852 ha->reset_tmplt.hdr->hdr_size;
853 qla4_83xx_dump_reset_seq_hdr(ha);
858 vfree(ha->reset_tmplt.buff);
867 * @ha : Pointer to adapter structure
871 static void qla4_83xx_read_write_crb_reg(struct scsi_qla_host *ha,
876 qla4_83xx_rd_reg_indirect(ha, raddr, &value);
877 qla4_83xx_wr_reg_indirect(ha, waddr, value);
886 * @ha : Pointer to adapter structure
891 static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr,
898 value = ha->reset_tmplt.array[p_rmw_hdr->index_a];
900 qla4_83xx_rd_reg_indirect(ha, raddr, &value);
908 qla4_83xx_wr_reg_indirect(ha, waddr, value);
913 static void qla4_83xx_write_list(struct scsi_qla_host *ha,
923 qla4_83xx_wr_reg_indirect(ha, p_entry->arg1, p_entry->arg2);
929 static void qla4_83xx_read_write_list(struct scsi_qla_host *ha,
939 qla4_83xx_read_write_crb_reg(ha, p_entry->arg1, p_entry->arg2);
945 static void qla4_83xx_poll_list(struct scsi_qla_host *ha,
965 qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
971 if (qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
974 qla4_83xx_rd_reg_indirect(ha, p_entry->arg1,
976 qla4_83xx_rd_reg_indirect(ha, p_entry->arg2,
983 static void qla4_83xx_poll_write_list(struct scsi_qla_host *ha,
998 qla4_83xx_wr_reg_indirect(ha, p_entry->dr_addr,
1000 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
1003 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
1006 DEBUG2(ql4_printk(KERN_INFO, ha,
1009 ha->reset_tmplt.seq_index));
1015 static void qla4_83xx_read_modify_write(struct scsi_qla_host *ha,
1028 qla4_83xx_rmw_crb_reg(ha, p_entry->arg1, p_entry->arg2,
1035 static void qla4_83xx_pause(struct scsi_qla_host *ha,
1042 static void qla4_83xx_poll_read_list(struct scsi_qla_host *ha,
1059 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
1062 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
1065 DEBUG2(ql4_printk(KERN_INFO, ha,
1068 ha->reset_tmplt.seq_index));
1070 index = ha->reset_tmplt.array_index;
1071 qla4_83xx_rd_reg_indirect(ha, p_entry->dr_addr,
1073 ha->reset_tmplt.array[index++] = value;
1076 ha->reset_tmplt.array_index = 1;
1082 static void qla4_83xx_seq_end(struct scsi_qla_host *ha,
1085 ha->reset_tmplt.seq_end = 1;
1088 static void qla4_83xx_template_end(struct scsi_qla_host *ha,
1091 ha->reset_tmplt.template_end = 1;
1093 if (ha->reset_tmplt.seq_error == 0) {
1094 DEBUG2(ql4_printk(KERN_INFO, ha,
1098 ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n",
1111 * @ha : Pointer to adapter structure
1114 static void qla4_83xx_process_reset_template(struct scsi_qla_host *ha,
1121 ha->reset_tmplt.seq_end = 0;
1122 ha->reset_tmplt.template_end = 0;
1123 entries = ha->reset_tmplt.hdr->entries;
1124 index = ha->reset_tmplt.seq_index;
1126 for (; (!ha->reset_tmplt.seq_end) && (index < entries); index++) {
1133 qla4_83xx_write_list(ha, p_hdr);
1136 qla4_83xx_read_write_list(ha, p_hdr);
1139 qla4_83xx_poll_list(ha, p_hdr);
1142 qla4_83xx_poll_write_list(ha, p_hdr);
1145 qla4_83xx_read_modify_write(ha, p_hdr);
1148 qla4_83xx_pause(ha, p_hdr);
1151 qla4_83xx_seq_end(ha, p_hdr);
1154 qla4_83xx_template_end(ha, p_hdr);
1157 qla4_83xx_poll_read_list(ha, p_hdr);
1160 ql4_printk(KERN_ERR, ha, "%s: Unknown command ==> 0x%04x on entry = %d\n",
1169 ha->reset_tmplt.seq_index = index;
1172 static void qla4_83xx_process_stop_seq(struct scsi_qla_host *ha)
1174 ha->reset_tmplt.seq_index = 0;
1175 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.stop_offset);
1177 if (ha->reset_tmplt.seq_end != 1)
1178 ql4_printk(KERN_ERR, ha, "%s: Abrupt STOP Sub-Sequence end.\n",
1182 static void qla4_83xx_process_start_seq(struct scsi_qla_host *ha)
1184 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.start_offset);
1186 if (ha->reset_tmplt.template_end != 1)
1187 ql4_printk(KERN_ERR, ha, "%s: Abrupt START Sub-Sequence end.\n",
1191 static void qla4_83xx_process_init_seq(struct scsi_qla_host *ha)
1193 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.init_offset);
1195 if (ha->reset_tmplt.seq_end != 1)
1196 ql4_printk(KERN_ERR, ha, "%s: Abrupt INIT Sub-Sequence end.\n",
1200 static int qla4_83xx_restart(struct scsi_qla_host *ha)
1205 qla4_83xx_process_stop_seq(ha);
1212 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
1214 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
1216 ql4_printk(KERN_INFO, ha, "%s: Graceful RESET: Not collecting minidump\n",
1219 qla4_8xxx_get_minidump(ha);
1222 qla4_83xx_process_init_seq(ha);
1224 if (qla4_83xx_copy_bootloader(ha)) {
1225 ql4_printk(KERN_ERR, ha, "%s: Copy bootloader, firmware restart failed!\n",
1231 qla4_83xx_wr_reg(ha, QLA83XX_FW_IMAGE_VALID, QLA83XX_BOOT_FROM_FLASH);
1232 qla4_83xx_process_start_seq(ha);
1238 int qla4_83xx_start_firmware(struct scsi_qla_host *ha)
1242 ret_val = qla4_83xx_restart(ha);
1244 ql4_printk(KERN_ERR, ha, "%s: Restart error\n", __func__);
1247 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Restart done\n",
1251 ret_val = qla4_83xx_check_cmd_peg_status(ha);
1253 ql4_printk(KERN_ERR, ha, "%s: Peg not initialized\n",
1262 static void qla4_83xx_disable_iocb_intrs(struct scsi_qla_host *ha)
1264 if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags))
1265 qla4_8xxx_intr_disable(ha);
1268 static void qla4_83xx_disable_mbox_intrs(struct scsi_qla_host *ha)
1272 if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
1273 ret = readl(&ha->qla4_83xx_reg->mbox_int);
1275 writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
1276 writel(1, &ha->qla4_83xx_reg->leg_int_mask);
1280 void qla4_83xx_disable_intrs(struct scsi_qla_host *ha)
1282 qla4_83xx_disable_mbox_intrs(ha);
1283 qla4_83xx_disable_iocb_intrs(ha);
1286 static void qla4_83xx_enable_iocb_intrs(struct scsi_qla_host *ha)
1288 if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) {
1289 qla4_8xxx_intr_enable(ha);
1290 set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags);
1294 void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha)
1298 if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
1300 writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
1301 writel(0, &ha->qla4_83xx_reg->leg_int_mask);
1302 set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags);
1307 void qla4_83xx_enable_intrs(struct scsi_qla_host *ha)
1309 qla4_83xx_enable_mbox_intrs(ha);
1310 qla4_83xx_enable_iocb_intrs(ha);
1314 void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
1321 writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]);
1323 writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]);
1328 writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr);
1331 void qla4_83xx_process_mbox_intr(struct scsi_qla_host *ha, int outcount)
1335 intr_status = readl(&ha->qla4_83xx_reg->risc_intr);
1337 ha->mbox_status_count = outcount;
1338 ha->isp_ops->interrupt_service_routine(ha, intr_status);
1344 * @ha: pointer to host adapter structure.
1346 int qla4_83xx_isp_reset(struct scsi_qla_host *ha)
1351 ha->isp_ops->idc_lock(ha);
1352 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
1355 qla4_83xx_set_idc_dontreset(ha);
1360 if (qla4_83xx_idc_dontreset(ha) == DONTRESET_BIT0) {
1361 ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n",
1367 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET\n",
1369 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
1379 DEBUG2(ql4_printk(KERN_INFO, ha,
1387 if (qla4_83xx_can_perform_reset(ha))
1388 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
1390 ha->isp_ops->idc_unlock(ha);
1391 rval = qla4_8xxx_device_state_handler(ha);
1393 ha->isp_ops->idc_lock(ha);
1394 qla4_8xxx_clear_rst_ready(ha);
1396 ha->isp_ops->idc_unlock(ha);
1399 clear_bit(AF_FW_RECOVERY, &ha->flags);
1404 static void qla4_83xx_dump_pause_control_regs(struct scsi_qla_host *ha)
1409 qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val);
1410 DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val));
1413 DEBUG2(ql4_printk(KERN_INFO, ha,
1416 qla4_83xx_rd_reg_indirect(ha,
1424 DEBUG2(ql4_printk(KERN_INFO, ha,
1427 qla4_83xx_rd_reg_indirect(ha,
1435 DEBUG2(ql4_printk(KERN_INFO, ha,
1438 qla4_83xx_rd_reg_indirect(ha,
1446 DEBUG2(ql4_printk(KERN_INFO, ha,
1449 qla4_83xx_rd_reg_indirect(ha,
1457 DEBUG2(ql4_printk(KERN_INFO, ha,
1460 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
1462 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS,
1464 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
1471 DEBUG2(ql4_printk(KERN_INFO, ha,
1474 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
1476 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS,
1478 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
1484 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS, &val);
1485 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS, &val1);
1487 DEBUG2(ql4_printk(KERN_INFO, ha,
1492 static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha)
1497 qla4_83xx_wr_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL,
1502 qla4_83xx_wr_reg_indirect(ha,
1506 qla4_83xx_wr_reg_indirect(ha,
1513 qla4_83xx_wr_reg_indirect(ha,
1517 qla4_83xx_wr_reg_indirect(ha,
1522 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS,
1524 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS,
1527 ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n");
1532 * @ha: Pointer to host adapter structure.
1538 static void qla4_83xx_eport_init(struct scsi_qla_host *ha)
1541 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0);
1542 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0);
1543 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0);
1544 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0);
1545 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0);
1546 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0);
1547 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0);
1548 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0);
1551 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF);
1553 ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n");
1556 void qla4_83xx_disable_pause(struct scsi_qla_host *ha)
1558 ha->isp_ops->idc_lock(ha);
1560 qla4_83xx_eport_init(ha);
1561 qla4_83xx_dump_pause_control_regs(ha);
1562 __qla4_83xx_disable_pause(ha);
1563 ha->isp_ops->idc_unlock(ha);
1568 * @ha: Pointer to host adapter structure.
1570 int qla4_83xx_is_detached(struct scsi_qla_host *ha)
1574 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1576 if (test_bit(AF_INIT_DONE, &ha->flags) &&
1577 !(drv_active & (1 << ha->func_num))) {
1578 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: drv_active = 0x%X\n",