scsi/qla2xxx/qla_dbg.c

73 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
75 	fw_dump->fw_major_version = htonl(ha->fw_major_version);
76 	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
77 	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
78 	fw_dump->fw_attributes = htonl(ha->fw_attributes);
80 	fw_dump->vendor = htonl(ha->pdev->vendor);
81 	fw_dump->device = htonl(ha->pdev->device);
82 	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
83 	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
87 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
89 	struct req_que *req = ha->req_q_map[0];
90 	struct rsp_que *rsp = ha->rsp_q_map[0];
104 qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
107 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
108 	dma_addr_t dump_dma = ha->gid_list_dma;
109 	uint32_t *chunk = (uint32_t *)ha->gid_list;
110 	uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
114 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
116 	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
140 		ha->flags.mbox_int = 0;
162 			set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
168 		ha->flags.mbox_int = 1;
171 		if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
181 			    (IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
191 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be32 *ram,
195 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
196 	dma_addr_t dump_dma = ha->gid_list_dma;
197 	uint32_t *chunk = (uint32_t *)ha->gid_list;
198 	uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
201 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
203 	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
226 		ha->flags.mbox_int = 0;
245 			set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
251 		ha->flags.mbox_int = 1;
254 		if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
264 				((IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
274 qla24xx_dump_memory(struct qla_hw_data *ha, __be32 *code_ram,
280 	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
284 	set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
287 	rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
288 	    ha->fw_memory_size - 0x100000 + 1, nxt);
290 		set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
310 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha)
317 		set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
321 qla24xx_soft_reset(struct qla_hw_data *ha)
326 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
341 		set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
345 	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
358 		set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
371 		set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
377 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be16 *ram,
383 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
384 	dma_addr_t dump_dma = ha->gid_list_dma;
385 	__le16 *dump = (__force __le16 *)ha->gid_list;
390 	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
391 	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
393 	words = qla2x00_gid_list_size(ha) / 2;
399 		WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
400 		WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
402 		WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
403 		WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
404 		WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
405 		WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
407 		WRT_MAILBOX_REG(ha, reg, 4, words);
418 					    &ha->mbx_cmd_flags);
420 					mb0 = RD_MAILBOX_REG(ha, reg, 0);
430 					    &ha->mbx_cmd_flags);
432 					mb0 = RD_MAILBOX_REG(ha, reg, 0);
447 		if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
472 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
474 	if (!ha->eft)
477 	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
478 	return ptr + ntohl(ha->fw_dump->eft_size);
482 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
488 	if (!ha->fce)
494 	    fce_calc_size(ha->fce_bufs));
495 	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
496 	fcec->addr_l = htonl(LSD(ha->fce_dma));
497 	fcec->addr_h = htonl(MSD(ha->fce_dma));
501 		*iter_reg++ = htonl(ha->fce_mb[cnt]);
503 	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
509 qla25xx_copy_exlogin(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
513 	if (!ha->exlogin_buf)
520 	    ha->exlogin_size);
521 	c->size = cpu_to_be32(ha->exlogin_size);
522 	c->addr = cpu_to_be64(ha->exlogin_buf_dma);
525 	memcpy(ptr, ha->exlogin_buf, ha->exlogin_size);
531 qla81xx_copy_exchoffld(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
535 	if (!ha->exchoffld_buf)
542 	    ha->exchoffld_size);
543 	c->size = cpu_to_be32(ha->exchoffld_size);
544 	c->addr = cpu_to_be64(ha->exchoffld_buf_dma);
547 	memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size);
553 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
565 	if (!ha->tgt.atio_ring)
570 	aqp->length = ha->tgt.atio_q_length;
571 	aqp->ring = ha->tgt.atio_ring;
574 		/* aqp = ha->atio_q_map[que]; */
601 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
609 	if (!ha->mqenable)
613 	for (que = 1; que < ha->max_req_queues; que++) {
614 		req = ha->req_q_map[que];
641 	for (que = 1; que < ha->max_rsp_queues; que++) {
642 		rsp = ha->rsp_q_map[que];
672 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
679 	if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
680 	    IS_QLA28XX(ha))
688 	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
689 		ha->max_req_queues : ha->max_rsp_queues;
692 		reg = ISP_QUE_REG(ha, cnt);
710 	struct qla_hw_data *ha = vha->hw;
715 		    rval, ha->fw_dump_cap_flags);
716 		ha->fw_dumped = false;
720 		    vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
721 		ha->fw_dumped = true;
744 	struct qla_hw_data *ha = vha->hw;
745 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
749 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
751 	lockdep_assert_held(&ha->hardware_lock);
753 	if (!ha->fw_dump) {
759 	if (ha->fw_dumped) {
763 		    ha->fw_dump);
766 	fw = &ha->fw_dump->isp.isp23;
767 	qla2xxx_prep_dump(ha, ha->fw_dump);
774 	if (IS_QLA2300(ha)) {
859 	if (!IS_QLA2300(ha)) {
860 		for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
871 		rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
876 		rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
881 		rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
882 		    ha->fw_memory_size - 0x11000 + 1, &nxt);
885 		qla2xxx_copy_queues(ha, nxt);
901 	struct qla_hw_data *ha = vha->hw;
902 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
905 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
907 	lockdep_assert_held(&ha->hardware_lock);
909 	if (!ha->fw_dump) {
915 	if (ha->fw_dumped) {
919 		    ha->fw_dump);
922 	fw = &ha->fw_dump->isp.isp21;
923 	qla2xxx_prep_dump(ha, ha->fw_dump);
943 		for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
996 	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
1005 	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
1019 			if (IS_QLA2100(ha))
1033  		WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
1034 		clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1038  		WRT_MAILBOX_REG(ha, reg, 1, risc_address);
1046 					    &ha->mbx_cmd_flags);
1048 					mb0 = RD_MAILBOX_REG(ha, reg, 0);
1049 					mb2 = RD_MAILBOX_REG(ha, reg, 2);
1063 		if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1072 		qla2xxx_copy_queues(ha, &fw->queue_dump[0]);
1082 	struct qla_hw_data *ha = vha->hw;
1083 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1091 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1093 	lockdep_assert_held(&ha->hardware_lock);
1095 	if (IS_P3P_TYPE(ha))
1098 	ha->fw_dump_cap_flags = 0;
1100 	if (!ha->fw_dump) {
1106 	if (ha->fw_dumped) {
1110 		    ha->fw_dump);
1113 	QLA_FW_STOPPED(ha);
1114 	fw = &ha->fw_dump->isp.isp24;
1115 	qla2xxx_prep_dump(ha, ha->fw_dump);
1123 	qla24xx_pause_risc(reg, ha);
1296 	rval = qla24xx_soft_reset(ha);
1300 	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1305 	nxt = qla2xxx_copy_queues(ha, nxt);
1307 	qla24xx_copy_eft(ha, nxt);
1309 	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1310 	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1312 		ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
1317 	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1328 	struct qla_hw_data *ha = vha->hw;
1329 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1336 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1338 	lockdep_assert_held(&ha->hardware_lock);
1340 	ha->fw_dump_cap_flags = 0;
1342 	if (!ha->fw_dump) {
1348 	if (ha->fw_dumped) {
1352 		    ha->fw_dump);
1355 	QLA_FW_STOPPED(ha);
1356 	fw = &ha->fw_dump->isp.isp25;
1357 	qla2xxx_prep_dump(ha, ha->fw_dump);
1358 	ha->fw_dump->version = htonl(2);
1366 	qla24xx_pause_risc(reg, ha);
1603 	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1606 	rval = qla24xx_soft_reset(ha);
1610 	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1615 	nxt = qla2xxx_copy_queues(ha, nxt);
1617 	qla24xx_copy_eft(ha, nxt);
1620 	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1621 	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1622 	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1623 	nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
1625 		ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
1630 	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1641 	struct qla_hw_data *ha = vha->hw;
1642 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1649 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1651 	lockdep_assert_held(&ha->hardware_lock);
1653 	ha->fw_dump_cap_flags = 0;
1655 	if (!ha->fw_dump) {
1661 	if (ha->fw_dumped) {
1665 		    ha->fw_dump);
1668 	fw = &ha->fw_dump->isp.isp81;
1669 	qla2xxx_prep_dump(ha, ha->fw_dump);
1677 	qla24xx_pause_risc(reg, ha);
1917 	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1920 	rval = qla24xx_soft_reset(ha);
1924 	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1929 	nxt = qla2xxx_copy_queues(ha, nxt);
1931 	qla24xx_copy_eft(ha, nxt);
1934 	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1935 	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1936 	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1937 	nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
1938 	nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain);
1940 		ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
1945 	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1956 	struct qla_hw_data *ha = vha->hw;
1957 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1964 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1966 	lockdep_assert_held(&ha->hardware_lock);
1968 	ha->fw_dump_cap_flags = 0;
1970 	if (!ha->fw_dump) {
1976 	if (ha->fw_dumped) {
1979 		    "request...\n", ha->fw_dump);
1982 	QLA_FW_STOPPED(ha);
1983 	fw = &ha->fw_dump->isp.isp83;
1984 	qla2xxx_prep_dump(ha, ha->fw_dump);
1992 	qla24xx_pause_risc(reg, ha);
2389 	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2392 	rval = qla24xx_soft_reset(ha);
2415 			nxt += (ha->fw_memory_size - 0x100000 + 1);
2418 			set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2424 	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2430 	nxt = qla2xxx_copy_queues(ha, nxt);
2432 	qla24xx_copy_eft(ha, nxt);
2435 	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2436 	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2437 	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2438 	nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
2439 	nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain);
2441 		ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
2446 	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2666 	struct qla_hw_data *ha = vha->hw;
2667 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2668 	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2669 	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2675 	if (IS_P3P_TYPE(ha))
2677 	else if (IS_FWI2_CAPABLE(ha))
2680 		mbx_reg = MAILBOX_REG(ha, reg, 0);