scsi/mvsas/mv_sas.c

12 static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
23 static void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
25 	void *bitmap = mvi->rsvd_tags;
29 static void mvs_tag_free(struct mvs_info *mvi, u32 tag)
34 	mvs_tag_clear(mvi, tag);
37 static void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
39 	void *bitmap = mvi->rsvd_tags;
43 static int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
46 	void *bitmap = mvi->rsvd_tags;
52 	mvs_tag_set(mvi, tag);
61 	struct mvs_info *mvi = NULL;
81 	mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
83 	return mvi;
91 	struct mvs_info *mvi = mvi_dev->mvi_info;
107 				phyno[n] = (j >= mvi->chip->n_phy) ?
108 					(j - mvi->chip->n_phy) : j;
120 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
125 		if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
128 		if (mvi->devices[dev_no].taskfileset == reg_set)
129 			return &mvi->devices[dev_no];
134 static inline void mvs_free_reg_set(struct mvs_info *mvi,
143 	MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
146 static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
151 	return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
154 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
160 		MVS_CHIP_DISP->phy_reset(mvi, no, hard);
170 	struct mvs_info *mvi = NULL;
178 	mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
182 		MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
186 		tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
189 		MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
193 		MVS_CHIP_DISP->phy_enable(mvi, phy_id);
194 		MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
198 		MVS_CHIP_DISP->phy_disable(mvi, phy_id);
208 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
214 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
215 	MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
216 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
217 	MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
220 static void mvs_bytes_dmaed(struct mvs_info *mvi, int i, gfp_t gfp_flags)
222 	struct mvs_phy *phy = &mvi->phy[i];
255 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
256 			MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
261 	mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
272 	struct mvs_info *mvi;
279 		mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
280 		for (i = 0; i < mvi->chip->n_phy; ++i)
281 			mvs_bytes_dmaed(mvi, i, GFP_KERNEL);
298 static int mvs_task_prep_smp(struct mvs_info *mvi,
302 	struct sas_ha_struct *sha = mvi->sas;
315 	struct mvs_slot_info *slot = &mvi->slot_info[tag];
322 	elem = dma_map_sg(mvi->dev, sg_req, 1, DMA_TO_DEVICE);
328 	elem = dma_map_sg(mvi->dev, sg_resp, 1, DMA_FROM_DEVICE);
372 	if (mvi->flags & MVF_FLAG_SOC)
378 	slot->tx = mvi->tx_prod;
379 	mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
401 	dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
404 	dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
427 static int mvs_task_prep_ata(struct mvs_info *mvi,
445 	if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
450 	slot = &mvi->slot_info[tag];
451 	slot->tx = mvi->tx_prod;
456 	mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
517 	if (mvi->flags & MVF_FLAG_SOC)
547 		MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
553 static int mvs_task_prep_ssp(struct mvs_info *mvi,
574 	slot = &mvi->slot_info[tag];
579 	slot->tx = mvi->tx_prod;
580 	mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
628 	if (mvi->flags & MVF_FLAG_SOC)
689 static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
749 			n_elem = dma_map_sg(mvi->dev,
766 		rc = mvs_tag_alloc(mvi, &tag);
771 	slot = &mvi->slot_info[tag];
777 	slot->buf = dma_pool_zalloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
784 	tei.hdr = &mvi->slot[tag];
789 		rc = mvs_task_prep_smp(mvi, &tei);
792 		rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
797 		rc = mvs_task_prep_ata(mvi, &tei);
800 		dev_printk(KERN_ERR, mvi->dev,
818 	mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
823 	dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
825 	mvs_tag_free(mvi, tag);
828 	dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
831 			dma_unmap_sg(mvi->dev, task->scatter, n_elem,
839 	struct mvs_info *mvi = NULL;
846 	mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
848 	spin_lock_irqsave(&mvi->lock, flags);
849 	rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
851 		dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
854 			MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
856 	spin_unlock_irqrestore(&mvi->lock, flags);
861 static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
864 	mvs_tag_free(mvi, slot_idx);
867 static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
876 			dma_unmap_sg(mvi->dev, task->scatter,
881 		dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
883 		dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
896 		dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
904 	mvs_slot_free(mvi, slot_idx);
907 static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
909 	struct mvs_phy *phy = &mvi->phy[phy_no];
915 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
917 			MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
920 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
922 			MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
928 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
931 	struct mvs_phy *phy = &mvi->phy[i];
934 	tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
946 			mvs_update_wideport(mvi, i);
956 static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
963 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
964 	s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
966 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
967 	s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
969 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
970 	s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
972 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
973 	s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
993 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
995 	struct mvs_phy *phy = &mvi->phy[i];
1001 		phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
1002 		phy->phy_status = mvs_is_phy_ready(mvi, i);
1007 		struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
1009 		oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1011 		MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1018 					i + mvi->id * mvi->chip->n_phy;
1023 				mvs_get_d2h_reg(mvi, i, id);
1026 				dev_printk(KERN_DEBUG, mvi->dev,
1028 				tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1029 				MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1056 			MVS_CHIP_DISP->phy_work_around(mvi, i);
1059 		i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1061 		i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
1064 		MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
1070 	struct mvs_info *mvi = NULL; int i = 0, hi;
1084 	mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1085 	if (i >= mvi->chip->n_phy)
1086 		port = &mvi->port[i - mvi->chip->n_phy];
1088 		port = &mvi->port[i];
1090 		spin_lock_irqsave(&mvi->lock, flags);
1097 		mvs_update_wideport(mvi, sas_phy->id);
1101 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
1102 			MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
1106 		spin_unlock_irqrestore(&mvi->lock, flags);
1113 	struct mvs_info *mvi = phy->mvi;
1117 	while (phy != &mvi->phy[phy_no]) {
1123 		mvs_do_release_task(phy->mvi, phy_no, dev);
1138 static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1142 		if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
1143 			mvi->devices[dev].device_id = dev;
1144 			return &mvi->devices[dev];
1169 	struct mvs_info *mvi = NULL;
1173 	mvi = mvs_find_dev_mvi(dev);
1176 		spin_lock_irqsave(&mvi->lock, flags);
1178 	mvi_device = mvs_alloc_dev(mvi);
1186 	mvi_device->mvi_info = mvi;
1205 		spin_unlock_irqrestore(&mvi->lock, flags);
1218 	struct mvs_info *mvi;
1225 	mvi = mvi_dev->mvi_info;
1227 	spin_lock_irqsave(&mvi->lock, flags);
1231 	mvs_release_task(mvi, dev);
1232 	mvs_free_reg_set(mvi, mvi_dev);
1238 	spin_unlock_irqrestore(&mvi->lock, flags);
1267 	struct mvs_info *mvi = mvi_dev->mvi_info;
1272 		spin_lock_irqsave(&mvi->lock, flags);
1273 		mvs_release_task(mvi, dev);
1274 		spin_unlock_irqrestore(&mvi->lock, flags);
1287 	struct mvs_info *mvi = mvi_dev->mvi_info;
1297 	spin_lock_irqsave(&mvi->lock, flags);
1298 	mvs_release_task(mvi, dev);
1299 	spin_unlock_irqrestore(&mvi->lock, flags);
1312 		struct mvs_info *mvi = mvi_dev->mvi_info;
1314 		rc = mvs_find_tag(mvi, task, &tag);
1339 	struct mvs_info *mvi;
1349 	mvi = mvi_dev->mvi_info;
1360 		rc = mvs_find_tag(mvi, task, &tag);
1376 				slot_no = (u32) (slot - mvi->slot_info);
1377 				spin_lock_irqsave(&mvi->lock, flags);
1378 				mvs_slot_complete(mvi, slot_no, 1);
1379 				spin_unlock_irqrestore(&mvi->lock, flags);
1387 			u32 slot_idx = (u32)(slot - mvi->slot_info);
1388 			mv_dprintk("mvs_abort_task() mvi=%p task=%p "
1390 				   mvi, task, slot, slot_idx);
1392 			mvs_slot_task_free(mvi, task, slot, slot_idx);
1404 static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1478 static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1481 	struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1489 		MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1491 	MVS_CHIP_DISP->command_active(mvi, slot_idx);
1502 			sas_ssp_task_response(mvi->dev, task, iu);
1519 		mvs_sata_done(mvi, task, slot_idx, err_dw0);
1529 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
1532 	struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1564 			mvs_free_reg_set(mvi, mvi_dev);
1566 		mvs_slot_task_free(mvi, task, slot, slot_idx);
1588 		tstat->stat = mvs_slot_err(mvi, task, slot_idx);
1604 			sas_ssp_task_response(mvi->dev, task, iu);
1623 			tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1641 			mvs_free_reg_set(mvi, mvi_dev);
1643 	mvs_slot_task_free(mvi, task, slot, slot_idx);
1646 	spin_unlock(&mvi->lock);
1650 	spin_lock(&mvi->lock);
1655 void mvs_do_release_task(struct mvs_info *mvi,
1663 	phy = &mvi->phy[phy_no];
1668 	mvs_int_rx(mvi, false);
1674 		slot_idx = (u32) (slot - mvi->slot_info);
1682 		MVS_CHIP_DISP->command_active(mvi, slot_idx);
1684 		mvs_slot_complete(mvi, slot_idx, 1);
1688 void mvs_release_task(struct mvs_info *mvi,
1694 		mvs_do_release_task(mvi, phyno[i], dev);
1708 	struct mvs_info *mvi = mwq->mvi;
1711 	struct mvs_phy *phy = &mvi->phy[phy_no];
1714 	spin_lock_irqsave(&mvi->lock, flags);
1720 			tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1729 				MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1730 				mvs_update_phyinfo(mvi, phy_no, 1);
1731 				mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
1743 	spin_unlock_irqrestore(&mvi->lock, flags);
1747 static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1754 		mwq->mvi = mvi;
1758 		list_add_tail(&mwq->entry, &mvi->wq_list);
1769 	struct mvs_info *mvi = phy->mvi;
1772 	for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
1773 		if (&mvi->phy[phy_no] == phy) {
1775 				phy_no+mvi->id*mvi->chip->n_phy);
1776 			MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
1781 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
1784 	struct mvs_phy *phy = &mvi->phy[phy_no];
1786 	phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
1787 	MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
1788 	mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
1789 		MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
1790 	mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
1800 		phy_no + mvi->id*mvi->chip->n_phy);
1808 			mvs_do_release_task(mvi, phy_no, NULL);
1810 			MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
1811 			mvs_handle_event(mvi,
1814 			ready = mvs_is_phy_ready(mvi, phy_no);
1817 					MVS_CHIP_DISP->stp_reset(mvi,
1820 					MVS_CHIP_DISP->phy_reset(mvi,
1828 		tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
1829 		MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
1838 		phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
1842 			MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1845 						mvi, phy_no);
1847 				MVS_CHIP_DISP->write_port_irq_mask(mvi,
1850 			mvs_update_phyinfo(mvi, phy_no, 0);
1852 				MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
1856 			mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
1864 				phy_no + mvi->id*mvi->chip->n_phy);
1868 			phy_no + mvi->id*mvi->chip->n_phy);
1869 		mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
1874 int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
1884 	rx_prod_idx = mvi->rx_cons;
1885 	mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
1886 	if (mvi->rx_cons == 0xfff)	/* h/w hasn't touched RX ring yet */
1893 	if (unlikely(mvi->rx_cons == rx_prod_idx))
1894 		mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
1896 	if (mvi->rx_cons == rx_prod_idx)
1899 	while (mvi->rx_cons != rx_prod_idx) {
1902 		rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
1905 			mvs_slot_complete(mvi, rx_desc, 0);
1910 				mvs_slot_complete(mvi, rx_desc, 0);
1912 			mvs_slot_free(mvi, rx_desc);
1917 		MVS_CHIP_DISP->int_full(mvi);
1925 	struct mvs_info *mvi = mvs_prv->mvi[0];