scsi/mvsas/mv_chips.h

28 static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
30 	void __iomem *regs = mvi->regs;
35 static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
37 	void __iomem *regs = mvi->regs;
42 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
44 	void __iomem *regs = mvi->regs;
49 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
51 	void __iomem *regs = mvi->regs;
58 static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
61 	void __iomem *regs = mvi->regs + off;
62 	void __iomem *regs2 = mvi->regs + off2;
67 static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
70 	void __iomem *regs = mvi->regs + off;
71 	void __iomem *regs2 = mvi->regs + off2;
78 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
80 	return mvs_read_port(mvi, MVS_P0_CFG_DATA,
84 static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
87 	mvs_write_port(mvi, MVS_P0_CFG_DATA,
91 static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
94 	mvs_write_port(mvi, MVS_P0_CFG_ADDR,
99 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
101 	return mvs_read_port(mvi, MVS_P0_VSR_DATA,
105 static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
108 	mvs_write_port(mvi, MVS_P0_VSR_DATA,
112 static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
115 	mvs_write_port(mvi, MVS_P0_VSR_ADDR,
120 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
122 	return mvs_read_port(mvi, MVS_P0_INT_STAT,
126 static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
129 	mvs_write_port(mvi, MVS_P0_INT_STAT,
133 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
135 	return mvs_read_port(mvi, MVS_P0_INT_MASK,
140 static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
143 	mvs_write_port(mvi, MVS_P0_INT_MASK,
147 static inline void mvs_phy_hacks(struct mvs_info *mvi)
151 	tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
154 	mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
157 	mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
160 	tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
163 	mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
165 	mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
168 	mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
171 static inline void mvs_int_sata(struct mvs_info *mvi)
174 	void __iomem *regs = mvi->regs;
178 	MVS_CHIP_DISP->clear_active_cmds(mvi);
181 static inline void mvs_int_full(struct mvs_info *mvi)
183 	void __iomem *regs = mvi->regs;
188 	mvs_int_rx(mvi, false);
190 	for (i = 0; i < mvi->chip->n_phy; i++) {
193 			mvs_int_port(mvi, i, tmp);
197 		MVS_CHIP_DISP->non_spec_ncq_error(mvi);
200 		mvs_int_sata(mvi);
205 static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
207 	void __iomem *regs = mvi->regs;
211 static inline u32 mvs_rx_update(struct mvs_info *mvi)
213 	void __iomem *regs = mvi->regs;
227 static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
235 	if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
238 	pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
242 	dev_printk(KERN_INFO, mvi->dev,