scsi/mvsas/mv_94xx.c

35 static void set_phy_tuning(struct mvs_info *mvi, int phy_id,
80 		mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
81 		tmp = mvs_read_port_vsr_data(mvi, phy_id);
86 		mvs_write_port_vsr_data(mvi, phy_id, tmp);
89 		mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
90 		tmp = mvs_read_port_vsr_data(mvi, phy_id);
93 		mvs_write_port_vsr_data(mvi, phy_id, tmp);
97 static void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
114 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
115 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
123 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
129 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
130 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
135 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
142 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
143 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
148 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
154 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
155 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
160 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
164 static void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
167 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
168 	phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
200 	mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
203 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
206 	temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
208 		mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
209 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
210 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
213 	temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
218 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
219 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
225 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
226 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
231 	temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
234 		mvi->hba_info_param.phy_rate[phy_id] = 0x2;
236 	set_phy_tuning(mvi, phy_id,
237 		mvi->hba_info_param.phy_tuning[phy_id]);
238 	set_phy_ffe_tuning(mvi, phy_id,
239 		mvi->hba_info_param.ffe_ctl[phy_id]);
240 	set_phy_rate(mvi, phy_id,
241 		mvi->hba_info_param.phy_rate[phy_id]);
244 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
250 	tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
254 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
259 		mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL);
260 		tmp = mvs_read_port_cfg_data(mvi, phy_id);
261 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000);
262 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000);
265 	tmp = mvs_read_port_irq_stat(mvi, phy_id);
267 	mvs_write_port_irq_stat(mvi, phy_id, tmp);
269 		tmp = mvs_read_phy_ctl(mvi, phy_id);
271 		mvs_write_phy_ctl(mvi, phy_id, tmp);
273 			tmp = mvs_read_phy_ctl(mvi, phy_id);
280 		tmp = mvs_read_phy_ctl(mvi, phy_id);
282 		mvs_write_phy_ctl(mvi, phy_id, tmp);
286 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
289 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
290 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
291 	mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
294 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
301 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
302 		mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
305 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
306 		mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
307 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
308 		mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
311 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
312 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
314 	mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
855 	att_dev_info |= (u32)id->phy_id<<24;
894 static void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
900 	tmp = mvs_read_phy_ctl(mvi, phy_id);
907 	mvs_write_phy_ctl(mvi, phy_id, tmp);
908 	mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);