scsi/mvsas/mv_94xx.c

14 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
17 	struct mvs_phy *phy = &mvi->phy[i];
20 	mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
21 	reg = mvs_read_port_vsr_data(mvi, i);
35 static void set_phy_tuning(struct mvs_info *mvi, int phy_id,
54 	if (mvi->pdev->revision == VANIR_A0_REV)
80 		mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
81 		tmp = mvs_read_port_vsr_data(mvi, phy_id);
86 		mvs_write_port_vsr_data(mvi, phy_id, tmp);
89 		mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
90 		tmp = mvs_read_port_vsr_data(mvi, phy_id);
93 		mvs_write_port_vsr_data(mvi, phy_id, tmp);
97 static void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
103 	if ((mvi->pdev->revision == VANIR_A0_REV)
104 		|| (mvi->pdev->revision == VANIR_B0_REV))
114 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
115 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
123 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
129 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
130 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
135 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
142 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
143 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
148 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
154 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
155 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
160 	mvs_write_port_vsr_data(mvi, phy_id, tmp);
164 static void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
167 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
168 	phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
200 	mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
203 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
206 	temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
208 		mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
209 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
210 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
213 	temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
215 		switch (mvi->pdev->revision) {
218 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
219 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
225 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
226 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
231 	temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
234 		mvi->hba_info_param.phy_rate[phy_id] = 0x2;
236 	set_phy_tuning(mvi, phy_id,
237 		mvi->hba_info_param.phy_tuning[phy_id]);
238 	set_phy_ffe_tuning(mvi, phy_id,
239 		mvi->hba_info_param.ffe_ctl[phy_id]);
240 	set_phy_rate(mvi, phy_id,
241 		mvi->hba_info_param.phy_rate[phy_id]);
244 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
246 	void __iomem *regs = mvi->regs;
254 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
259 		mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL);
260 		tmp = mvs_read_port_cfg_data(mvi, phy_id);
261 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000);
262 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000);
265 	tmp = mvs_read_port_irq_stat(mvi, phy_id);
267 	mvs_write_port_irq_stat(mvi, phy_id, tmp);
269 		tmp = mvs_read_phy_ctl(mvi, phy_id);
271 		mvs_write_phy_ctl(mvi, phy_id, tmp);
273 			tmp = mvs_read_phy_ctl(mvi, phy_id);
280 		tmp = mvs_read_phy_ctl(mvi, phy_id);
282 		mvs_write_phy_ctl(mvi, phy_id, tmp);
286 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
289 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
290 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
291 	mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
294 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
299 	revision = mvi->pdev->revision;
301 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
302 		mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
305 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
306 		mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
307 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
308 		mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
311 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
312 	tmp = mvs_read_port_vsr_data(mvi, phy_id);
314 	mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
317 static void mvs_94xx_sgpio_init(struct mvs_info *mvi)
319 	void __iomem *regs = mvi->regs_ex - 0x10200;
326 	mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
329 	mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id,
338 	mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id,
343 	mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id,
351 	mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
354 	mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id,
355 		((mvi->id * 4) + 3) << (8 * 3) |
356 		((mvi->id * 4) + 2) << (8 * 2) |
357 		((mvi->id * 4) + 1) << (8 * 1) |
358 		((mvi->id * 4) + 0) << (8 * 0));
362 static int mvs_94xx_init(struct mvs_info *mvi)
364 	void __iomem *regs = mvi->regs;
369 	revision = mvi->pdev->revision;
370 	mvs_show_pcie_usage(mvi);
371 	if (mvi->flags & MVF_FLAG_SOC) {
386 	if (mvi->flags & MVF_FLAG_SOC) {
427 	mvs_phy_hacks(mvi);
430 	tmp = mvs_cr32(mvi, CMD_SAS_CTL1);
436 		mvs_cw32(mvi, CMD_SAS_CTL1, tmp);
446 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
447 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
449 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
450 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
453 	mw32(MVS_TX_LO, mvi->tx_dma);
454 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
457 	mw32(MVS_RX_LO, mvi->rx_dma);
458 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
460 	for (i = 0; i < mvi->chip->n_phy; i++) {
461 		mvs_94xx_phy_disable(mvi, i);
463 		mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
464 						cpu_to_le64(mvi->phy[i].dev_sas_addr));
466 		mvs_94xx_enable_xmt(mvi, i);
467 		mvs_94xx_config_reg_from_hba(mvi, i);
468 		mvs_94xx_phy_enable(mvi, i);
470 		mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);
472 		mvs_94xx_detect_porttype(mvi, i);
475 	if (mvi->flags & MVF_FLAG_SOC) {
486 	for (i = 0; i < mvi->chip->n_phy; i++) {
488 		tmp = mvs_read_port_irq_stat(mvi, i);
490 		mvs_write_port_irq_stat(mvi, i, tmp);
495 		mvs_write_port_irq_mask(mvi, i, tmp);
498 		mvs_update_phyinfo(mvi, i, 1);
541 	tmp = mvs_cr32(mvi, CMD_LINK_TIMER);
543 	mvs_cw32(mvi, CMD_LINK_TIMER, tmp);
547 	mvs_cw32(mvi, CMD_PL_TIMER, tmp);
550 	tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1);
552 	mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp);
556 	tmp = mvs_cr32(mvi, CMD_SL_MODE0);
560 	mvs_cw32(mvi, CMD_SL_MODE0, tmp);
565 	mvs_94xx_sgpio_init(mvi);
570 static int mvs_94xx_ioremap(struct mvs_info *mvi)
572 	if (!mvs_ioremap(mvi, 2, -1)) {
573 		mvi->regs_ex = mvi->regs + 0x10200;
574 		mvi->regs += 0x20000;
575 		if (mvi->id == 1)
576 			mvi->regs += 0x4000;
582 static void mvs_94xx_iounmap(struct mvs_info *mvi)
584 	if (mvi->regs) {
585 		mvi->regs -= 0x20000;
586 		if (mvi->id == 1)
587 			mvi->regs -= 0x4000;
588 		mvs_iounmap(mvi->regs);
592 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
594 	void __iomem *regs = mvi->regs_ex;
607 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
609 	void __iomem *regs = mvi->regs_ex;
623 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
625 	void __iomem *regs = mvi->regs_ex;
627 	if (!(mvi->flags & MVF_FLAG_SOC)) {
636 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
638 	void __iomem *regs = mvi->regs;
640 	if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) ||
641 			((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) {
644 		spin_lock(&mvi->lock);
645 		mvs_int_full(mvi);
646 		spin_unlock(&mvi->lock);
651 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
654 	tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));
657 		mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),
660 			tmp = mvs_cr32(mvi,
667 mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
669 	void __iomem *regs = mvi->regs;
699 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
702 	void __iomem *regs = mvi->regs;
704 	mvs_94xx_clear_srs_irq(mvi, 0, 1);
712 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi)
714 	void __iomem *regs = mvi->regs;
726 			device = mvs_find_dev_by_reg_set(mvi, i);
728 				mvs_release_task(mvi, device->sas_device);
731 			device = mvs_find_dev_by_reg_set(mvi, i+32);
733 				mvs_release_task(mvi, device->sas_device);
741 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
743 	void __iomem *regs = mvi->regs;
749 	mvi->sata_reg_set &= ~bit(reg_set);
751 		w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
753 		w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32));
760 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
763 	void __iomem *regs = mvi->regs;
768 	i = mv_ffc64(mvi->sata_reg_set);
770 		mvi->sata_reg_set |= bit(i);
771 		w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
775 		mvi->sata_reg_set |= bit(i);
776 		w_reg_set_enable(i, (u32)mvi->sata_reg_set);
798 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
801 	phy_st = mvs_read_phy_ctl(mvi, i);
807 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
814 		mvs_write_port_cfg_addr(mvi, port_id,
816 		id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
821 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
828 		mvs_write_port_cfg_addr(mvi, port_id,
830 		id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
832 			port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
864 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
867 	struct mvs_phy *phy = &mvi->phy[i];
877 	mvs_94xx_get_dev_identify_frame(mvi, i, id);
881 		mvs_94xx_get_att_identify_frame(mvi, i, id);
889 	mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
890 	mvs_write_port_cfg_data(mvi, i, 0x04);
894 static void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
900 	tmp = mvs_read_phy_ctl(mvi, phy_id);
907 	mvs_write_phy_ctl(mvi, phy_id, tmp);
908 	mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);
911 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
914 	void __iomem *regs = mvi->regs;
924 static u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
926 	void __iomem *regs = mvi->regs_ex - 0x10200;
930 static void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
932 	void __iomem *regs = mvi->regs_ex - 0x10200;
938 static int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
946 	void __iomem *regs = mvi->regs_ex - 0x10200;
963 static int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
965 	void __iomem *regs = mvi->regs_ex - 0x10200;
971 static int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
973 	void __iomem *regs = mvi->regs_ex - 0x10200;
986 static void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
998 	if ((mvi->pdev->revision == VANIR_A0_REV) ||
999 			(mvi->pdev->revision == VANIR_B0_REV))
1001 				mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1;
1018 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)
1020 	void __iomem *regs = mvi->regs;
1063 			struct mvs_info *mvi = mvs_prv->mvi[i/(4*3)];
1065 			void __iomem *regs = mvi->regs_ex - 0x10200;
1070 				MVS_SGPIO_HOST_OFFSET * mvi->id);
1106 				MVS_SGPIO_HOST_OFFSET * mvi->id);
1117 			struct mvs_info *mvi = mvs_prv->mvi[i+reg_index];
1118 			void __iomem *regs = mvi->regs_ex - 0x10200;
1120 			mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,