scsi/mvsas/mv_64xx.c

31 	u32 tmp;
33 	tmp = mr32(MVS_PCS);
35 		tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
37 		tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
38 	mw32(MVS_PCS, tmp);
70 	u32 reg, tmp;
81 	tmp = reg;
83 		tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
85 		tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;
89 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
93 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
98 		mw32(MVS_PHY_CTL, tmp);
106 	u32 tmp;
107 	tmp = mvs_read_port_irq_stat(mvi, phy_id);
108 	tmp &= ~PHYEV_RDY_CH;
109 	mvs_write_port_irq_stat(mvi, phy_id, tmp);
110 	tmp = mvs_read_phy_ctl(mvi, phy_id);
112 		tmp |= PHY_RST_HARD;
114 		tmp |= PHY_RST;
115 	mvs_write_phy_ctl(mvi, phy_id, tmp);
118 			tmp = mvs_read_phy_ctl(mvi, phy_id);
119 		} while (tmp & PHY_RST_HARD);
127 	u32 tmp;
129 		tmp = mr32(MVS_INT_STAT_SRS_0);
130 		if (tmp) {
131 			printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);
132 			mw32(MVS_INT_STAT_SRS_0, tmp);
135 		tmp = mr32(MVS_INT_STAT_SRS_0);
136 		if (tmp &  (1 << (reg_set % 32))) {
147 	u32 tmp;
152 	tmp = mr32(MVS_GBL_CTL);
155 	if (!(tmp & HBA_RST)) {
157 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
158 			tmp &= ~PCTL_PWR_OFF;
159 			tmp |= PCTL_PHY_DSBL;
160 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
162 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
163 			tmp &= ~PCTL_PWR_OFF;
164 			tmp |= PCTL_PHY_DSBL;
165 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
171 	tmp = mr32(MVS_GBL_CTL);
174 	if (!(tmp & HBA_RST)) {
197 	u32 tmp;
206 		pci_read_config_dword(mvi->pdev, offs, &tmp);
207 		tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
208 		pci_write_config_dword(mvi->pdev, offs, tmp);
210 		tmp = mr32(MVS_PHY_CTL);
211 		tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
212 		mw32(MVS_PHY_CTL, tmp);
219 	u32 tmp;
228 		pci_read_config_dword(mvi->pdev, offs, &tmp);
229 		tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
230 		pci_write_config_dword(mvi->pdev, offs, tmp);
232 		tmp = mr32(MVS_PHY_CTL);
233 		tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
234 		mw32(MVS_PHY_CTL, tmp);
242 	u32 tmp, cctl;
248 		tmp = mvs_64xx_chip_reset(mvi);
249 		if (tmp)
250 			return tmp;
252 		tmp = mr32(MVS_PHY_CTL);
253 		tmp &= ~PCTL_PWR_OFF;
254 		tmp |= PCTL_PHY_DSBL;
255 		mw32(MVS_PHY_CTL, tmp);
268 		pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
269 		tmp &= ~PRD_REQ_MASK;
270 		tmp |= PRD_REQ_SIZE;
271 		pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
273 		pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
274 		tmp &= ~PCTL_PWR_OFF;
275 		tmp &= ~PCTL_PHY_DSBL;
276 		pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
278 		pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
279 		tmp &= PCTL_PWR_OFF;
280 		tmp &= ~PCTL_PHY_DSBL;
281 		pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
283 		tmp = mr32(MVS_PHY_CTL);
284 		tmp &= ~PCTL_PWR_OFF;
285 		tmp |= PCTL_COM_ON;
286 		tmp &= ~PCTL_PHY_DSBL;
287 		tmp |= PCTL_LINK_RST;
288 		mw32(MVS_PHY_CTL, tmp);
290 		tmp &= ~PCTL_LINK_RST;
291 		mw32(MVS_PHY_CTL, tmp);
300 	tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
301 	tmp &= 0x0000ffff;
302 	tmp |= 0x00fa0000;
303 	mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
347 		tmp = mvs_read_port_irq_stat(mvi, i);
348 		tmp &= ~PHYEV_SIG_FIS;
349 		mvs_write_port_irq_stat(mvi, i, tmp);
352 		tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
355 		mvs_write_port_irq_mask(mvi, i, tmp);
370 	tmp = mr32(MVS_PCS);
371 	tmp |= PCS_CMD_RST;
372 	tmp &= ~PCS_SELF_CLEAR;
373 	mw32(MVS_PCS, tmp);
378 	tmp = 0;
384 	tmp = 0x10000 | interrupt_coalescing;
385 	mw32(MVS_INT_COAL_TMOUT, tmp);
396 	tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
399 	mw32(MVS_INT_MASK, tmp);
423 	u32 tmp;
425 	tmp = mr32(MVS_GBL_CTL);
426 	mw32(MVS_GBL_CTL, tmp | INT_EN);
432 	u32 tmp;
434 	tmp = mr32(MVS_GBL_CTL);
435 	mw32(MVS_GBL_CTL, tmp & ~INT_EN);
469 	u32 tmp;
473 		tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
474 	} while (tmp & 1 << (slot_idx % 32));
476 		tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
477 	} while (tmp & 1 << (slot_idx % 32));
484 	u32 tmp;
487 		tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
488 		mw32(MVS_INT_STAT_SRS_0, tmp);
491 	tmp = mr32(MVS_PCS) | 0xFF00;
492 	mw32(MVS_PCS, tmp);
498 	u32 tmp, offs;
505 		tmp = mr32(MVS_PCS);
506 		mw32(MVS_PCS, tmp & ~offs);
508 		tmp = mr32(MVS_CTL);
509 		mw32(MVS_CTL, tmp & ~offs);
512 	tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
513 	if (tmp)
514 		mw32(MVS_INT_STAT_SRS_0, tmp);
523 	u32 tmp, offs;
529 	tmp = mr32(MVS_PCS);
533 			tmp = mr32(MVS_CTL);
535 		if (!(tmp & offs)) {
539 				mw32(MVS_PCS, tmp | offs);
541 				mw32(MVS_CTL, tmp | offs);
542 			tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
543 			if (tmp)
544 				mw32(MVS_INT_STAT_SRS_0, tmp);
608 	u32 tmp;
611 	tmp = mvs_read_port_vsr_data(mvi, i);
615 		tmp &= ~PHY_MODE6_LATECLK;
617 		tmp |= PHY_MODE6_LATECLK;
618 	mvs_write_port_vsr_data(mvi, i, tmp);
625 	u32 tmp;
627 	tmp = mvs_read_phy_ctl(mvi, phy_id);
632 		tmp &= ~(0xf << 8);
633 		tmp |= lrmin;
636 		tmp &= ~(0xf << 12);
637 		tmp |= lrmax;
639 	mvs_write_phy_ctl(mvi, phy_id, tmp);
645 	u32 tmp;
647 	tmp = mr32(MVS_PCS);
648 	mw32(MVS_PCS, tmp & 0xFFFF);
649 	mw32(MVS_PCS, tmp);
650 	tmp = mr32(MVS_CTL);
651 	mw32(MVS_CTL, tmp & 0xFFFF);
652 	mw32(MVS_CTL, tmp);
742 	u32 tmp = 0;
756 		tmp = 0x10000 | time;
757 		mw32(MVS_INT_COAL_TMOUT, tmp);