Lines Matching defs:mvi
14 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
16 void __iomem *regs = mvi->regs;
18 struct mvs_phy *phy = &mvi->phy[i];
28 static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
30 void __iomem *regs = mvi->regs;
34 if (mvi->chip->n_phy <= MVS_SOC_PORTS)
41 static void mvs_64xx_phy_hacks(struct mvs_info *mvi)
43 void __iomem *regs = mvi->regs;
46 mvs_phy_hacks(mvi);
48 if (!(mvi->flags & MVF_FLAG_SOC)) {
50 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8);
51 mvs_write_port_vsr_data(mvi, i, 0x2F0);
56 for (i = 0; i < mvi->chip->n_phy; i++) {
57 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
58 mvs_write_port_vsr_data(mvi, i, 0x90000000);
59 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
60 mvs_write_port_vsr_data(mvi, i, 0x50f2);
61 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
62 mvs_write_port_vsr_data(mvi, i, 0x0e);
67 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
69 void __iomem *regs = mvi->regs;
72 if (!(mvi->flags & MVF_FLAG_SOC)) {
74 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
76 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
87 if (!(mvi->flags & MVF_FLAG_SOC)) {
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
91 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
93 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
95 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
104 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
107 tmp = mvs_read_port_irq_stat(mvi, phy_id);
109 mvs_write_port_irq_stat(mvi, phy_id, tmp);
110 tmp = mvs_read_phy_ctl(mvi, phy_id);
115 mvs_write_phy_ctl(mvi, phy_id, tmp);
118 tmp = mvs_read_phy_ctl(mvi, phy_id);
124 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
126 void __iomem *regs = mvi->regs;
144 static int mvs_64xx_chip_reset(struct mvs_info *mvi)
146 void __iomem *regs = mvi->regs;
156 if (mvi->flags & MVF_PHY_PWR_FIX) {
157 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
160 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
162 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
165 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
188 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
194 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
196 void __iomem *regs = mvi->regs;
198 if (!(mvi->flags & MVF_FLAG_SOC)) {
206 pci_read_config_dword(mvi->pdev, offs, &tmp);
208 pci_write_config_dword(mvi->pdev, offs, tmp);
216 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
218 void __iomem *regs = mvi->regs;
220 if (!(mvi->flags & MVF_FLAG_SOC)) {
228 pci_read_config_dword(mvi->pdev, offs, &tmp);
230 pci_write_config_dword(mvi->pdev, offs, tmp);
238 static int mvs_64xx_init(struct mvs_info *mvi)
240 void __iomem *regs = mvi->regs;
244 if (mvi->pdev && mvi->pdev->revision == 0)
245 mvi->flags |= MVF_PHY_PWR_FIX;
246 if (!(mvi->flags & MVF_FLAG_SOC)) {
247 mvs_show_pcie_usage(mvi);
248 tmp = mvs_64xx_chip_reset(mvi);
266 if (!(mvi->flags & MVF_FLAG_SOC)) {
268 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
271 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
273 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
276 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
278 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
281 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
298 mvs_64xx_phy_hacks(mvi);
300 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
303 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
308 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
309 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
311 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
312 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
315 mw32(MVS_TX_LO, mvi->tx_dma);
316 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
319 mw32(MVS_RX_LO, mvi->rx_dma);
320 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
322 for (i = 0; i < mvi->chip->n_phy; i++) {
325 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
326 cpu_to_be64(mvi->phy[i].dev_sas_addr));
328 mvs_64xx_enable_xmt(mvi, i);
330 mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);
332 mvs_64xx_detect_porttype(mvi, i);
334 if (mvi->flags & MVF_FLAG_SOC) {
345 for (i = 0; i < mvi->chip->n_phy; i++) {
347 tmp = mvs_read_port_irq_stat(mvi, i);
349 mvs_write_port_irq_stat(mvi, i, tmp);
355 mvs_write_port_irq_mask(mvi, i, tmp);
358 mvs_update_phyinfo(mvi, i, 1);
407 static int mvs_64xx_ioremap(struct mvs_info *mvi)
409 if (!mvs_ioremap(mvi, 4, 2))
414 static void mvs_64xx_iounmap(struct mvs_info *mvi)
416 mvs_iounmap(mvi->regs);
417 mvs_iounmap(mvi->regs_ex);
420 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
422 void __iomem *regs = mvi->regs;
429 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
431 void __iomem *regs = mvi->regs;
438 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
440 void __iomem *regs = mvi->regs;
443 if (!(mvi->flags & MVF_FLAG_SOC)) {
453 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
455 void __iomem *regs = mvi->regs;
460 spin_lock(&mvi->lock);
461 mvs_int_full(mvi);
462 spin_unlock(&mvi->lock);
467 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
470 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
471 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
473 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
476 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
480 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
483 void __iomem *regs = mvi->regs;
495 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
497 void __iomem *regs = mvi->regs;
520 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
524 void __iomem *regs = mvi->regs;
531 for (i = 0; i < mvi->chip->srs_sz; i++) {
563 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
566 mvs_write_port_cfg_addr(mvi, i,
568 phy_st = mvs_read_port_cfg_data(mvi, i);
574 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
578 struct mvs_phy *phy = &mvi->phy[i];
592 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
593 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
595 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
596 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
598 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
600 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
601 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
602 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
606 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
609 struct mvs_phy *phy = &mvi->phy[i];
610 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
611 tmp = mvs_read_port_vsr_data(mvi, i);
618 mvs_write_port_vsr_data(mvi, i, tmp);
621 static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
627 tmp = mvs_read_phy_ctl(mvi, phy_id);
639 mvs_write_phy_ctl(mvi, phy_id, tmp);
640 mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);
643 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
646 void __iomem *regs = mvi->regs;
656 static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
658 void __iomem *regs = mvi->regs_ex;
662 static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
664 void __iomem *regs = mvi->regs_ex;
670 static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
694 static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
696 void __iomem *regs = mvi->regs_ex;
709 static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
711 void __iomem *regs = mvi->regs_ex;
724 static void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
729 dma_addr_t buf_dma = mvi->bulk_buffer_dma;
739 static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time)
741 void __iomem *regs = mvi->regs;