Lines Matching defs:rc
125 int i = 0, rc;
158 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
160 if (rc != MBX_SUCCESS) {
183 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
184 if (rc != MBX_SUCCESS) {
247 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
249 if (rc != MBX_SUCCESS) {
427 int rc;
446 rc = lpfc_read_sparam(phba, pmb, 0);
447 if (rc) {
551 rc = lpfc_config_msi(phba, pmb);
552 if (rc) {
556 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
557 if (rc != MBX_SUCCESS) {
614 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
615 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
618 " mbox command rc 0x%x\n", rc);
625 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
626 if (rc)
627 return rc;
639 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
641 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
645 rc);
659 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
661 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
664 "to get Option ROM version status x%x\n", rc);
684 int length, rc;
698 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
699 if (unlikely(rc)) {
701 return rc;
720 return rc;
765 int rc;
803 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
804 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
818 if (rc != MBX_BUSY || flag == MBX_POLL)
846 int rc;
858 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
859 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
862 " mbox command rc 0x%x\n", rc);
1906 int rc;
1916 rc = lpfc_sli4_pdev_status_reg_wait(phba);
1917 if (rc)
1918 return rc;
1949 rc = lpfc_sli_brdrestart(phba);
1950 if (rc) {
1953 return rc;
1963 rc = lpfc_online(phba);
1964 if (rc == 0)
1967 return rc;
1991 int rc, i;
2051 rc = lpfc_sli4_port_sta_fn_reset(phba,
2053 if (rc == 0)
2127 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
2129 if (rc == 0) {
2189 int rc = 0;
2193 rc = 1;
2197 rc = lpfc_mbox_rsrc_prep(phba, pmb);
2198 if (rc) {
2199 rc = 2;
2212 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
2213 if (rc == MBX_NOT_FINISHED) {
2214 rc = 4;
2246 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
4059 int rc;
4082 rc = -ENOMEM;
4094 rc = -ENOMEM;
4146 rc = -ENOMEM;
4156 return rc;
4178 int rc;
4202 rc = -ENOMEM;
4214 rc = -ENOMEM;
4271 rc = -ENOMEM;
4281 return rc;
4398 int rc, cnt;
4448 rc = -ENOMEM;
4459 return rc;
4584 int rc;
4595 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4596 if (rc != MBX_SUCCESS) {
4701 int rc;
4708 rc = lpfc_sli_chipset_init(phba);
4709 if (rc)
4818 rc = lpfc_vmid_res_alloc(phba, vport);
4820 if (rc)
5418 int rc;
5431 rc = lpfc_mbox_rsrc_prep(phba, pmb);
5432 if (rc) {
5485 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5486 if (rc == MBX_NOT_FINISHED)
6223 int rc;
6324 rc = lpfc_mbox_rsrc_prep(phba, pmb);
6325 if (rc) {
6384 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
6385 if (rc == MBX_NOT_FINISHED)
6413 int rc, i, cnt;
6541 rc = lpfc_sli4_read_config(phba);
6542 if (rc) {
6547 "speeds, rc = 0x%x\n", rc);
6549 rc = lpfc_sli4_refresh_params(phba);
6550 if (rc) {
6553 "rc x%x\n", rc);
6732 int rc;
6768 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
6793 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
6795 if (rc)
6798 "command failed (x%x)\n", rc);
6847 rc = lpfc_sli4_redisc_fcf_table(phba);
6848 if (rc) {
6938 rc = lpfc_sli4_redisc_fcf_table(phba);
6939 if (rc) {
7371 int rc;
7385 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
7386 if (rc)
7389 "command failed 0x%x\n", rc);
7405 int rc;
7415 rc = lpfc_init_api_table_setup(phba, dev_grp);
7416 if (rc)
7419 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
7420 if (rc)
7423 rc = lpfc_sli_api_table_setup(phba, dev_grp);
7424 if (rc)
7427 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
7428 if (rc)
7547 int rc = 0;
7561 rc = lpfc_pci_function_reset(phba);
7569 if (unlikely(rc)) {
7571 "8888 PCI function reset failed rc %x\n",
7572 rc);
7621 int rc;
7631 rc = pci_enable_sriov(pdev, nr_vfn);
7632 if (rc) {
7635 "with vfn number nr_vf:%d, rc:%d\n",
7636 nr_vfn, rc);
7641 return rc;
7748 int rc, entry_sz;
7765 rc = lpfc_setup_driver_resource_phase1(phba);
7766 if (rc)
7862 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
7864 if (rc) {
7916 int rc, i, max_buf_size;
7931 rc = lpfc_setup_driver_resource_phase1(phba);
7932 if (rc)
7936 rc = lpfc_sli4_post_status_check(phba);
7937 if (rc)
8050 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
8051 if (rc)
8057 rc = lpfc_pci_function_reset(phba);
8058 if (unlikely(rc)) {
8059 rc = -ENODEV;
8066 rc = lpfc_create_bootstrap_mbox(phba);
8067 if (unlikely(rc))
8071 rc = lpfc_setup_endian_order(phba);
8072 if (unlikely(rc))
8076 rc = lpfc_sli4_read_config(phba);
8077 if (unlikely(rc))
8091 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
8092 if (unlikely(rc))
8098 rc = lpfc_pci_function_reset(phba);
8099 if (unlikely(rc))
8106 rc = -ENOMEM;
8116 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8117 if (rc != MBX_SUCCESS) {
8125 rc = -EIO;
8180 rc = lpfc_get_sli4_parameters(phba, mboxq);
8181 if (rc) {
8194 rc = -EIO;
8201 rc = -EIO;
8315 rc = -ENOMEM;
8326 rc = -ENOMEM;
8339 rc = lpfc_sli4_queue_verify(phba);
8340 if (rc)
8344 rc = lpfc_sli4_cq_event_pool_create(phba);
8345 if (rc)
8352 rc = lpfc_init_active_sgl_array(phba);
8353 if (rc) {
8358 rc = lpfc_sli4_init_rpi_hdrs(phba);
8359 if (rc) {
8373 rc = -ENOMEM;
8384 rc = -ENOMEM;
8395 rc = -ENOMEM;
8403 rc = -ENOMEM;
8413 rc = -ENOMEM;
8422 rc = -ENOMEM;
8431 rc = -ENOMEM;
8440 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
8442 if (rc) {
8487 return rc;
8863 int rc = 0;
8868 return rc;
8877 rc = -ENODEV;
8880 return rc;
9919 int length, i, rc = 0, rc2;
9931 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
9932 if (rc != MBX_SUCCESS) {
9938 rc = -EIO;
10124 if (rc)
10255 return rc;
10275 uint32_t if_type, rc = 0;
10298 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10299 if (rc != MBX_SUCCESS) {
10303 rc);
10304 rc = -EIO;
10314 return rc;
10954 int rc;
10964 rc = lpfc_cq_create(phba, cq, eq,
10966 if (rc) {
10968 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
10969 qidx, (uint32_t)rc);
10970 return rc;
10983 rc = lpfc_wq_create(phba, wq, cq, qtype);
10984 if (rc) {
10986 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
10987 qidx, (uint32_t)rc);
10989 return rc;
11001 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
11002 if (rc) {
11005 "rc = 0x%x\n", rc);
11007 return rc;
11073 int rc = -ENOMEM;
11089 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11095 if (shdr_status || shdr_add_status || rc) {
11099 shdr_status, shdr_add_status, rc);
11101 rc = -ENXIO;
11127 rc = -ENOMEM;
11146 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
11148 if (rc) {
11151 " EQ (%d), rc = 0x%x\n",
11152 cpup->eq, (uint32_t)rc);
11173 rc = lpfc_create_wq_cq(phba,
11180 if (rc) {
11183 "IO WQ/CQ (%d), rc = 0x%x\n",
11184 qidx, (uint32_t)rc);
11200 rc = -ENOMEM;
11204 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
11208 if (rc) {
11210 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
11211 (uint32_t)rc);
11219 rc = -ENOMEM;
11223 rc = lpfc_cq_create_set(phba,
11227 if (rc) {
11230 "Set, rc = 0x%x\n",
11231 (uint32_t)rc);
11236 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
11239 if (rc) {
11242 "rc = 0x%x\n", (uint32_t)rc);
11260 rc = -ENOMEM;
11263 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
11267 if (rc) {
11269 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
11270 (uint32_t)rc);
11284 rc = -ENOMEM;
11287 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
11291 if (rc) {
11294 "rc = 0x%x\n", (uint32_t)rc);
11315 rc = -ENOMEM;
11319 rc = lpfc_mrq_create(phba,
11324 if (rc) {
11327 "MRQ: rc = 0x%x\n",
11328 (uint32_t)rc);
11333 rc = lpfc_rq_create(phba,
11338 if (rc) {
11341 "Receive Queue: rc = 0x%x\n",
11342 (uint32_t)rc);
11360 rc = -ENOMEM;
11364 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
11366 if (rc) {
11369 "rc = 0x%x\n", (uint32_t)rc);
11398 rc = -ENOMEM;
11408 return rc;
11683 uint32_t rc = 0, if_type;
11708 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11715 if (shdr_status || shdr_add_status || rc) {
11720 shdr_status, shdr_add_status, rc);
11721 rc = -ENXIO;
11735 rc = -ENODEV;
11754 rc = -ENODEV;
11780 rc = -ENODEV;
11792 if (rc) {
11796 rc = -ENODEV;
11799 return rc;
12075 int rc;
12079 rc = pci_alloc_irq_vectors(phba->pcidev,
12081 if (rc < 0) {
12083 "0420 PCI enable MSI-X failed (%d)\n", rc);
12092 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
12095 if (rc) {
12098 "(%d)\n", rc);
12103 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
12107 if (rc) {
12110 "(%d)\n", rc);
12120 rc = -ENOMEM;
12126 rc = lpfc_config_msi(phba, pmb);
12127 if (rc)
12129 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
12130 if (rc != MBX_SUCCESS) {
12140 return rc;
12159 return rc;
12179 int rc;
12181 rc = pci_enable_msi(phba->pcidev);
12182 if (!rc)
12187 "0471 PCI enable MSI mode failed (%d)\n", rc);
12188 return rc;
12191 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
12193 if (rc) {
12196 "0478 MSI request_irq failed (%d)\n", rc);
12198 return rc;
12988 int vectors, rc, index;
13016 rc = pci_alloc_irq_vectors(phba->pcidev, 1, vectors, flags);
13017 if (rc < 0) {
13019 "0484 PCI enable MSI-X failed (%d)\n", rc);
13022 vectors = rc;
13033 rc = pci_irq_vector(phba->pcidev, index);
13034 if (rc < 0) {
13037 "pci_irq_vec failed (%d)\n", index, rc);
13040 eqhdl->irq = rc;
13042 rc = request_threaded_irq(eqhdl->irq,
13046 if (rc) {
13049 "request_irq failed (%d)\n", index, rc);
13110 return rc;
13124 return rc;
13144 int rc, index;
13148 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
13150 if (rc > 0)
13155 "0488 PCI enable MSI mode failed (%d)\n", rc);
13156 return rc ? rc : -1;
13159 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
13161 if (rc) {
13164 "0490 MSI request_irq failed (%d)\n", rc);
13165 return rc;
13169 rc = pci_irq_vector(phba->pcidev, 0);
13170 if (rc < 0) {
13173 "0496 MSI pci_irq_vec failed (%d)\n", rc);
13174 return rc;
13176 eqhdl->irq = rc;
13649 int length, rc;
13680 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
13687 if (shdr_status || shdr_add_status || rc) {
13692 shdr_status, shdr_add_status, rc, reg);
13726 int rc;
13748 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
13751 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
13753 if (unlikely(rc))
13754 return rc;
13794 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
13797 if (rc) {
13864 rc = dma_set_max_seg_size(&phba->pcidev->dev, sli4_params->sge_supp_len);
13865 if (unlikely(rc)) {
13868 return rc;
14551 int rc;
14574 rc = -EINVAL;
14583 rc = -EACCES;
14591 rc = -EIO;
14593 return rc;
14609 int i, rc = 0;
14616 rc = -ENXIO;
14637 rc = -ENOMEM;
14646 rc = -ENOMEM;
14665 rc = lpfc_wr_object(phba, &dma_buffer_list,
14667 if (rc) {
14668 rc = lpfc_log_write_firmware_error(phba, offset,
14677 rc = offset;
14693 if (rc < 0)
14695 "3062 Firmware update error, status %d.\n", rc);
14698 "3024 Firmware update success: size %d.\n", rc);
15374 int rc;
15382 rc = lpfc_pci_probe_one_s4(pdev, pid);
15384 rc = lpfc_pci_probe_one_s3(pdev, pid);
15386 return rc;
15439 int rc = -ENODEV;
15443 rc = lpfc_pci_suspend_one_s3(dev);
15446 rc = lpfc_pci_suspend_one_s4(dev);
15454 return rc;
15475 int rc = -ENODEV;
15479 rc = lpfc_pci_resume_one_s3(dev);
15482 rc = lpfc_pci_resume_one_s4(dev);
15490 return rc;
15513 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15521 rc = lpfc_io_error_detected_s3(pdev, state);
15524 rc = lpfc_io_error_detected_s4(pdev, state);
15532 return rc;
15554 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15558 rc = lpfc_io_slot_reset_s3(pdev);
15561 rc = lpfc_io_slot_reset_s4(pdev);
15569 return rc;