Lines Matching refs:__be64
247 __be64 endian_ctrl; /* Per context Endian Control. The AFU will
252 __be64 intr_status; /* this sends LISN# programmed in ctx_ctrl.
282 __be64 intr_clear;
283 __be64 intr_mask;
284 __be64 ioarrin; /* only write what cmd_room permits */
285 __be64 rrq_start; /* start & end are both inclusive */
286 __be64 rrq_end; /* write sequence: start followed by end */
287 __be64 cmd_room;
288 __be64 ctx_ctrl; /* least significant byte or b56:63 is LISN# */
291 __be64 mbox_w; /* restricted use */
292 __be64 sq_start; /* Submission Queue (R/W): write sequence and */
293 __be64 sq_end; /* inclusion semantics are the same as RRQ */
294 __be64 sq_head; /* Submission Queue Head (R): for debugging */
295 __be64 sq_tail; /* Submission Queue TAIL (R/W): next IOARCB */
296 __be64 sq_ctx_reset; /* Submission Queue Context Reset (R/W) */
301 __be64 rht_start;
302 __be64 rht_cnt_id;
306 __be64 ctx_cap; /* afu_rc below is when the capability is violated */
315 __be64 mbox_r;
316 __be64 lisn_pasid[2];
319 __be64 lisn_ea[3];
324 __be64 aintr_status;
387 __be64 aintr_clear;
388 __be64 aintr_mask;
389 __be64 afu_ctrl;
390 __be64 afu_hb;
391 __be64 afu_scratch_pad;
392 __be64 afu_port_sel;
411 __be64 afu_config;
412 __be64 rsvd[0xf8];
414 __be64 interface_version;
438 __be64 fc_port_regs[CXLFLASH_NUM_FC_PORTS_PER_BANK][CXLFLASH_NUM_REGS];
439 __be64 fc_port_luns[CXLFLASH_NUM_FC_PORTS_PER_BANK][CXLFLASH_NUM_VLUNS];