scsi/bfa/bfa_ioc_cb.c

138 	void __iomem *rb;
141 	rb = bfa_ioc_bar0(ioc);
143 	ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
144 	ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
145 	ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
148 		ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
149 		ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
150 		ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
152 		ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
153 		ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
154 		ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
160 	ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
161 	ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
166 	ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
167 	ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
168 	ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
169 	ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
174 	ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
175 	ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
180 	ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
186 	ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
357 bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
369 	join_bits = readl(rb + BFA_IOC0_STATE_REG) &
371 	writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG));
372 	join_bits = readl(rb + BFA_IOC1_STATE_REG) &
374 	writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG));
375 	writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
376 	writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
377 	writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
378 	writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
379 	writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
380 	writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
381 	writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
383 			rb + APP_PLL_SCLK_CTL_REG);
384 	writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
386 			rb + APP_PLL_LCLK_CTL_REG);
388 	writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
389 	writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
391 			rb + APP_PLL_SCLK_CTL_REG);
393 			rb + APP_PLL_LCLK_CTL_REG);
395 	writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
396 	writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
397 	writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
398 	writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));