drivers/scsi/advansys.c

925 	ushort sdtr_able;	/* 04 Synchronous DTR able */
1811 	ushort sdtr_able;	/* try SDTR for a device */
2358 	printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2359 	       (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
3056 				   (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3305 	ushort sdtr_able, wdtr_able;
3406 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3416 			   (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3430 		    ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
4366 	ushort wdtr_able = 0, sdtr_able, tagqng_able;
4414 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4513 				 asc_dvc->sdtr_able);
4765 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4810 	ushort wdtr_able, sdtr_able, tagqng_able;
4845 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5030 				 asc_dvc->sdtr_able);
5251 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5296 	ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5332 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5525 				 asc_dvc->sdtr_able);
5744 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5773 	ushort wdtr_able, sdtr_able, tagqng_able;
5785 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5842 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7309  * 'sdtr_able' bit. Write the new value to the microcode.
7362 		if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
9253 	0xFFFF,			/* sdtr_able */
9291 	0,			/* sdtr_able */
10002 	asc_dvc->sdtr_able = eep_config.sdtr_able;
10174 	 * are set, then set an 'sdtr_able' bit for it.
10176 	asc_dvc->sdtr_able = 0;
10188 			asc_dvc->sdtr_able |= (1 << tid);
10398 	 * are set, then set an 'sdtr_able' bit for it.
10400 	asc_dvc->sdtr_able = 0;
10412 			asc_dvc->sdtr_able |= (1 << tid);
10890 			ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;