Lines Matching refs:RESET
489 #define RESET BIT(7)
1739 if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
1744 (FIFO | TIMEOUT | RESET | SCAM_SEL));
2003 (BUS_FREE | RESET))) {
2009 else if (p_int & RESET) {
2722 (PHASE | RESET))
2804 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
3720 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET)) &&
3740 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
3751 if (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
3827 if (RDW_HARPOON((port + hp_intstat)) & RESET) {
3854 (BUS_FREE | ICMD_COMP | ITAR_DISC | RESET))) {
4000 if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
4043 if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
4519 WRW_HARPOON(map_addr, RAT_OP); /*RESET ATTENTION */
6096 (RESET | TIMEOUT | SEL | BUS_FREE | AUTO_INT));
6105 (RESET | PROG_HLT | TIMEOUT | AUTO_INT))) {
6108 if (RDW_HARPOON((p_port + hp_intstat)) & RESET)
6119 if (RDW_HARPOON((p_port + hp_intstat)) & (RESET | TIMEOUT)) {
6122 (RESET | TIMEOUT | SEL | BUS_FREE | PHASE));
6426 FPT_default_intena = RESET | RSEL | PROG_HLT | TIMEOUT |