drivers/reset/reset-npcm.c

101 	struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
104 	writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
115 	struct npcm_rc_data *rc = to_rc_data(rcdev);
121 	spin_lock_irqsave(&rc->lock, flags);
122 	stat = readl(rc->base + ctrl_offset);
124 		writel(stat | rst_bit, rc->base + ctrl_offset);
126 		writel(stat & ~rst_bit, rc->base + ctrl_offset);
127 	spin_unlock_irqrestore(&rc->lock, flags);
146 	struct npcm_rc_data *rc = to_rc_data(rcdev);
150 	return (readl(rc->base + ctrl_offset) & rst_bit);
156 	struct npcm_rc_data *rc = to_rc_data(rcdev);
162 	for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) {
163 		if (offset == rc->info->ipsrst[off_num]) {
189 static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
197 	regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
215 	iprst1 = readl(rc->base + NPCM_IPSRST1);
216 	iprst2 = readl(rc->base + NPCM_IPSRST2);
217 	iprst3 = readl(rc->base + NPCM_IPSRST3);
224 	writel(iprst1, rc->base + NPCM_IPSRST1);
225 	writel(iprst2, rc->base + NPCM_IPSRST2);
226 	writel(iprst3, rc->base + NPCM_IPSRST3);
229 	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
231 	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
236 	writel(iprst3, rc->base + NPCM_IPSRST3);
241 	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
243 	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
251 	writel(iprst1, rc->base + NPCM_IPSRST1);
252 	writel(iprst2, rc->base + NPCM_IPSRST2);
253 	writel(iprst3, rc->base + NPCM_IPSRST3);
256 static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
265 	regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
285 	iprst1 = readl(rc->base + NPCM_IPSRST1);
286 	iprst2 = readl(rc->base + NPCM_IPSRST2);
287 	iprst3 = readl(rc->base + NPCM_IPSRST3);
288 	iprst4 = readl(rc->base + NPCM_IPSRST4);
296 	writel(iprst1, rc->base + NPCM_IPSRST1);
297 	writel(iprst2, rc->base + NPCM_IPSRST2);
298 	writel(iprst3, rc->base + NPCM_IPSRST3);
299 	writel(iprst4, rc->base + NPCM_IPSRST4);
302 	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
304 	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
306 	regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
311 	writel(iprst3, rc->base + NPCM_IPSRST3);
313 	writel(iprst4, rc->base + NPCM_IPSRST4);
316 	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
318 	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
320 	regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
329 	writel(iprst1, rc->base + NPCM_IPSRST1);
330 	writel(iprst2, rc->base + NPCM_IPSRST2);
331 	writel(iprst3, rc->base + NPCM_IPSRST3);
332 	writel(iprst4, rc->base + NPCM_IPSRST4);
339 static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
343 	rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
344 	if (IS_ERR(rc->gcr_regmap)) {
347 		rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
348 		if (IS_ERR(rc->gcr_regmap)) {
350 			return PTR_ERR(rc->gcr_regmap);
354 	rc->info = device_get_match_data(dev);
355 	switch (rc->info->bmc_id) {
357 		npcm_usb_reset_npcm7xx(rc);
360 		npcm_usb_reset_npcm8xx(rc);
377 	struct npcm_rc_data *rc;
380 	rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
381 	if (!rc)
384 	rc->base = devm_platform_ioremap_resource(pdev, 0);
385 	if (IS_ERR(rc->base))
386 		return PTR_ERR(rc->base);
388 	spin_lock_init(&rc->lock);
390 	rc->rcdev.owner = THIS_MODULE;
391 	rc->rcdev.ops = &npcm_rc_ops;
392 	rc->rcdev.of_node = pdev->dev.of_node;
393 	rc->rcdev.of_reset_n_cells = 2;
394 	rc->rcdev.of_xlate = npcm_reset_xlate;
396 	ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
402 	if (npcm_usb_reset(pdev, rc))
406 				  &rc->sw_reset_number)) {
407 		if (rc->sw_reset_number && rc->sw_reset_number < 5) {
408 			rc->restart_nb.priority = 192,
409 			rc->restart_nb.notifier_call = npcm_rc_restart,
410 			ret = register_restart_handler(&rc->restart_nb);