drivers/remoteproc/qcom_q6v5_adsp.c

118 	int (*shutdown)(struct qcom_adsp *adsp);
121 static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names,
124 	struct device *dev = adsp->dev;
138 	ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list);
147 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp)
149 	struct device *dev = adsp->dev;
150 	struct dev_pm_domain_list *pds = adsp->pd_list;
155 		pm_runtime_disable(adsp->dev);
158 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp)
160 	struct device *dev = adsp->dev;
161 	struct dev_pm_domain_list *pds = adsp->pd_list;
189 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp)
191 	struct device *dev = adsp->dev;
192 	struct dev_pm_domain_list *pds = adsp->pd_list;
209 static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
213 	regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
216 	regmap_read_poll_timeout(adsp->halt_map,
217 				 adsp->halt_lpass + LPASS_HALTACK_REG, val,
221 	reset_control_assert(adsp->pdc_sync_reset);
224 	reset_control_assert(adsp->restart);
230 	reset_control_deassert(adsp->restart);
233 	reset_control_deassert(adsp->pdc_sync_reset);
237 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
239 	regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
242 	regmap_read_poll_timeout(adsp->halt_map,
243 				 adsp->halt_lpass + LPASS_HALTACK_REG, val,
249 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
256 	val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
258 	writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
260 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
263 	ret = regmap_read(adsp->halt_map,
264 			adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
268 	ret = regmap_read(adsp->halt_map,
269 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
274 	regmap_write(adsp->halt_map,
275 			adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
280 		ret = regmap_read(adsp->halt_map,
281 			adsp->halt_lpass + LPASS_HALTACK_REG, &val);
288 	ret = regmap_read(adsp->halt_map,
289 			adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
291 		dev_err(adsp->dev, "port failed halt\n");
295 	reset_control_assert(adsp->pdc_sync_reset);
297 	reset_control_assert(adsp->restart);
302 	regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
305 	reset_control_deassert(adsp->pdc_sync_reset);
307 	reset_control_deassert(adsp->restart);
316 	struct qcom_adsp *adsp = rproc->priv;
319 	ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
320 				    adsp->mem_region, adsp->mem_phys,
321 				    adsp->mem_size, &adsp->mem_reloc);
325 	qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
332 	struct qcom_adsp *adsp = rproc->priv;
334 	if (adsp->has_iommu)
335 		iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);
340 	struct qcom_adsp *adsp = rproc->priv;
346 	if (!adsp->has_iommu)
352 	ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
359 	iova =  adsp->mem_phys | (sid << 32);
361 	ret = iommu_map(rproc->domain, iova, adsp->mem_phys,
362 			adsp->mem_size,	IOMMU_READ | IOMMU_WRITE,
365 		dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
374 	struct qcom_adsp *adsp = rproc->priv;
378 	ret = qcom_q6v5_prepare(&adsp->q6v5);
384 		dev_err(adsp->dev, "ADSP smmu mapping failed\n");
388 	ret = clk_prepare_enable(adsp->xo);
392 	ret = qcom_rproc_pds_enable(adsp);
396 	ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
398 		dev_err(adsp->dev, "adsp clk_enable failed\n");
403 	writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
406 	writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
409 	writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
412 	writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
414 	if (adsp->lpass_efuse)
415 		writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
418 	writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
421 	writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
424 	ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
427 		dev_err(adsp->dev, "failed to bootup adsp\n");
431 	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
433 		dev_err(adsp->dev, "start timed out\n");
440 	clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
442 	qcom_rproc_pds_disable(adsp);
444 	clk_disable_unprepare(adsp->xo);
448 	qcom_q6v5_unprepare(&adsp->q6v5);
455 	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
457 	clk_disable_unprepare(adsp->xo);
458 	qcom_rproc_pds_disable(adsp);
463 	struct qcom_adsp *adsp = rproc->priv;
467 	ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
469 		dev_err(adsp->dev, "timed out on wait\n");
471 	ret = adsp->shutdown(adsp);
473 		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
477 	handover = qcom_q6v5_unprepare(&adsp->q6v5);
479 		qcom_adsp_pil_handover(&adsp->q6v5);
486 	struct qcom_adsp *adsp = rproc->priv;
489 	offset = da - adsp->mem_reloc;
490 	if (offset < 0 || offset + len > adsp->mem_size)
493 	return adsp->mem_region + offset;
498 	struct qcom_adsp *adsp = rproc->priv;
507 	if (adsp->has_iommu) {
519 	struct qcom_adsp *adsp = rproc->priv;
521 	return qcom_q6v5_panic(&adsp->q6v5);
533 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
538 	adsp->xo = devm_clk_get(adsp->dev, "xo");
539 	if (IS_ERR(adsp->xo)) {
540 		ret = PTR_ERR(adsp->xo);
542 			dev_err(adsp->dev, "failed to get xo clock");
549 	adsp->num_clks = num_clks;
550 	adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
551 				sizeof(*adsp->clks), GFP_KERNEL);
552 	if (!adsp->clks)
555 	for (i = 0; i < adsp->num_clks; i++)
556 		adsp->clks[i].id = clk_ids[i];
558 	return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
561 static int adsp_init_reset(struct qcom_adsp *adsp)
563 	adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
565 	if (IS_ERR(adsp->pdc_sync_reset)) {
566 		dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
567 		return PTR_ERR(adsp->pdc_sync_reset);
570 	adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
573 	if (!adsp->restart)
574 		adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
576 	if (IS_ERR(adsp->restart)) {
577 		dev_err(adsp->dev, "failed to acquire restart\n");
578 		return PTR_ERR(adsp->restart);
584 static int adsp_init_mmio(struct qcom_adsp *adsp,
591 	adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
592 	if (IS_ERR(adsp->qdsp6ss_base)) {
593 		dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
594 		return PTR_ERR(adsp->qdsp6ss_base);
599 		adsp->lpass_efuse = NULL;
600 		dev_dbg(adsp->dev, "failed to get efuse memory region\n");
602 		adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
603 		if (IS_ERR(adsp->lpass_efuse)) {
604 			dev_err(adsp->dev, "failed to map efuse registers\n");
605 			return PTR_ERR(adsp->lpass_efuse);
614 	adsp->halt_map = syscon_node_to_regmap(syscon);
616 	if (IS_ERR(adsp->halt_map))
617 		return PTR_ERR(adsp->halt_map);
620 			1, &adsp->halt_lpass);
629 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
634 	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
640 		dev_err(adsp->dev, "unable to resolve memory-region\n");
644 	adsp->mem_phys = adsp->mem_reloc = rmem->base;
645 	adsp->mem_size = rmem->size;
646 	adsp->mem_region = devm_ioremap_wc(adsp->dev,
647 				adsp->mem_phys, adsp->mem_size);
648 	if (!adsp->mem_region) {
649 		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
650 			&rmem->base, adsp->mem_size);
661 	struct qcom_adsp *adsp;
678 				 firmware_name, sizeof(*adsp));
688 	adsp = rproc->priv;
689 	adsp->dev = &pdev->dev;
690 	adsp->rproc = rproc;
691 	adsp->info_name = desc->sysmon_name;
692 	adsp->has_iommu = desc->has_iommu;
694 	platform_set_drvdata(pdev, adsp);
697 		adsp->shutdown = qcom_wpss_shutdown;
699 		adsp->shutdown = qcom_adsp_shutdown;
701 	ret = adsp_alloc_memory_region(adsp);
705 	ret = adsp_init_clock(adsp, desc->clk_ids);
709 	ret = qcom_rproc_pds_attach(adsp, desc->pd_names, desc->num_pds);
715 	ret = adsp_init_reset(adsp);
719 	ret = adsp_init_mmio(adsp, pdev);
723 	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
728 	qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
729 	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
730 	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
733 	if (IS_ERR(adsp->sysmon)) {
734 		ret = PTR_ERR(adsp->sysmon);
745 	qcom_rproc_pds_detach(adsp);
752 	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
754 	rproc_del(adsp->rproc);
756 	qcom_q6v5_deinit(&adsp->q6v5);
757 	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
758 	qcom_remove_sysmon_subdev(adsp->sysmon);
759 	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
760 	qcom_rproc_pds_detach(adsp);
765 	.firmware_name = "adsp.mdt",
767 	.sysmon_name = "adsp",
782 	.firmware_name = "adsp.pbn",
783 	.load_state = "adsp",
785 	.sysmon_name = "adsp",
831 	{ .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
833 	{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },