Lines Matching refs:mbox
628 int mbox;
630 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
631 tsi721_omsg_handler(priv, mbox);
647 int mbox;
649 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
650 tsi721_imsg_handler(priv, mbox + 4);
1687 * @mbox: Outbound mailbox
1694 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
1702 if (!priv->omsg_init[mbox] ||
1706 spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags);
1708 tx_slot = priv->omsg_ring[mbox].tx_slot;
1711 memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len);
1717 desc = priv->omsg_ring[mbox].omd_base;
1725 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) |
1728 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] &
1731 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32);
1733 priv->omsg_ring[mbox].wr_count++;
1736 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1737 priv->omsg_ring[mbox].tx_slot = 0;
1739 priv->omsg_ring[mbox].wr_count++;
1745 iowrite32(priv->omsg_ring[mbox].wr_count,
1746 priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1747 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1749 spin_unlock_irqrestore(&priv->omsg_ring[mbox].lock, flags);
1897 * @mbox: Mailbox to open
1903 int mbox, int entries)
1911 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1916 if ((mbox_sel & (1 << mbox)) == 0) {
1921 priv->omsg_ring[mbox].dev_id = dev_id;
1922 priv->omsg_ring[mbox].size = entries;
1923 priv->omsg_ring[mbox].sts_rdptr = 0;
1924 spin_lock_init(&priv->omsg_ring[mbox].lock);
1929 priv->omsg_ring[mbox].omq_base[i] =
1932 &priv->omsg_ring[mbox].omq_phys[i],
1934 if (priv->omsg_ring[mbox].omq_base[i] == NULL) {
1936 "ENOMEM for OB_MSG_%d data buffer", mbox);
1943 priv->omsg_ring[mbox].omd_base = dma_alloc_coherent(
1946 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL);
1947 if (priv->omsg_ring[mbox].omd_base == NULL) {
1949 "ENOMEM for OB_MSG_%d descriptor memory", mbox);
1954 priv->omsg_ring[mbox].tx_slot = 0;
1957 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1958 priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev,
1959 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1960 &priv->omsg_ring[mbox].sts_phys,
1962 if (priv->omsg_ring[mbox].sts_base == NULL) {
1964 "ENOMEM for OB_MSG_%d status FIFO", mbox);
1974 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1975 priv->regs + TSI721_OBDMAC_DPTRH(mbox));
1976 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1978 priv->regs + TSI721_OBDMAC_DPTRL(mbox));
1981 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1982 priv->regs + TSI721_OBDMAC_DSBH(mbox));
1983 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1985 priv->regs + TSI721_OBDMAC_DSBL(mbox));
1986 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
1987 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox));
1993 int idx = TSI721_VECT_OMB0_DONE + mbox;
2002 mbox);
2006 idx = TSI721_VECT_OMB0_INT + mbox;
2012 "Unable to get MSI-X IRQ for MBOX%d-INT", mbox);
2013 idx = TSI721_VECT_OMB0_DONE + mbox;
2020 tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL);
2023 bd_ptr = priv->omsg_ring[mbox].omd_base;
2027 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys &
2030 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32);
2031 priv->omsg_ring[mbox].wr_count = 0;
2036 priv->regs + TSI721_OBDMAC_CTL(mbox));
2037 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
2040 priv->omsg_init[mbox] = 1;
2047 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
2048 priv->omsg_ring[mbox].sts_base,
2049 priv->omsg_ring[mbox].sts_phys);
2051 priv->omsg_ring[mbox].sts_base = NULL;
2057 priv->omsg_ring[mbox].omd_base,
2058 priv->omsg_ring[mbox].omd_phys);
2060 priv->omsg_ring[mbox].omd_base = NULL;
2063 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2064 if (priv->omsg_ring[mbox].omq_base[i]) {
2067 priv->omsg_ring[mbox].omq_base[i],
2068 priv->omsg_ring[mbox].omq_phys[i]);
2070 priv->omsg_ring[mbox].omq_base[i] = NULL;
2081 * @mbox: Mailbox to close
2083 static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox)
2088 if (!priv->omsg_init[mbox])
2090 priv->omsg_init[mbox] = 0;
2094 tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL);
2098 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
2100 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
2107 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
2108 priv->omsg_ring[mbox].sts_base,
2109 priv->omsg_ring[mbox].sts_phys);
2111 priv->omsg_ring[mbox].sts_base = NULL;
2115 (priv->omsg_ring[mbox].size + 1) *
2117 priv->omsg_ring[mbox].omd_base,
2118 priv->omsg_ring[mbox].omd_phys);
2120 priv->omsg_ring[mbox].omd_base = NULL;
2123 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2124 if (priv->omsg_ring[mbox].omq_base[i]) {
2127 priv->omsg_ring[mbox].omq_base[i],
2128 priv->omsg_ring[mbox].omq_phys[i]);
2130 priv->omsg_ring[mbox].omq_base[i] = NULL;
2144 u32 mbox = ch - 4;
2148 spin_lock(&priv->imsg_ring[mbox].lock);
2153 tsi_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout", mbox);
2156 tsi_info(&priv->pdev->dev, "IB MBOX%d PCIe error", mbox);
2159 tsi_info(&priv->pdev->dev, "IB MBOX%d IB free queue low", mbox);
2166 mport->inb_msg[mbox].mcback)
2167 mport->inb_msg[mbox].mcback(mport,
2168 priv->imsg_ring[mbox].dev_id, mbox, -1);
2179 spin_unlock(&priv->imsg_ring[mbox].lock);
2186 * @mbox: Mailbox to open
2192 int mbox, int entries)
2195 int ch = mbox + 4;
2202 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
2207 if ((mbox_sel & (1 << mbox)) == 0) {
2213 priv->imsg_ring[mbox].dev_id = dev_id;
2214 priv->imsg_ring[mbox].size = entries;
2215 priv->imsg_ring[mbox].rx_slot = 0;
2216 priv->imsg_ring[mbox].desc_rdptr = 0;
2217 priv->imsg_ring[mbox].fq_wrptr = 0;
2218 for (i = 0; i < priv->imsg_ring[mbox].size; i++)
2219 priv->imsg_ring[mbox].imq_base[i] = NULL;
2220 spin_lock_init(&priv->imsg_ring[mbox].lock);
2223 priv->imsg_ring[mbox].buf_base =
2226 &priv->imsg_ring[mbox].buf_phys,
2229 if (priv->imsg_ring[mbox].buf_base == NULL) {
2231 "Failed to allocate buffers for IB MBOX%d", mbox);
2237 priv->imsg_ring[mbox].imfq_base =
2240 &priv->imsg_ring[mbox].imfq_phys,
2243 if (priv->imsg_ring[mbox].imfq_base == NULL) {
2245 "Failed to allocate free queue for IB MBOX%d", mbox);
2251 priv->imsg_ring[mbox].imd_base =
2254 &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL);
2256 if (priv->imsg_ring[mbox].imd_base == NULL) {
2259 mbox);
2265 free_ptr = priv->imsg_ring[mbox].imfq_base;
2268 (u64)(priv->imsg_ring[mbox].buf_phys) +
2285 * Configure Inbound Messaging channel (ch = mbox + 4)
2289 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
2291 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
2298 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
2300 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
2310 int idx = TSI721_VECT_IMB0_RCV + mbox;
2319 mbox);
2323 idx = TSI721_VECT_IMB0_INT + mbox;
2329 "Unable to get MSI-X IRQ for IBOX%d-INT", mbox);
2331 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2344 priv->imsg_ring[mbox].fq_wrptr = entries - 1;
2347 priv->imsg_init[mbox] = 1;
2353 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2354 priv->imsg_ring[mbox].imd_base,
2355 priv->imsg_ring[mbox].imd_phys);
2357 priv->imsg_ring[mbox].imd_base = NULL;
2362 priv->imsg_ring[mbox].size * 8,
2363 priv->imsg_ring[mbox].imfq_base,
2364 priv->imsg_ring[mbox].imfq_phys);
2366 priv->imsg_ring[mbox].imfq_base = NULL;
2370 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2371 priv->imsg_ring[mbox].buf_base,
2372 priv->imsg_ring[mbox].buf_phys);
2374 priv->imsg_ring[mbox].buf_base = NULL;
2383 * @mbox: Mailbox to close
2385 static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox)
2389 int ch = mbox + 4;
2391 if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */
2393 priv->imsg_init[mbox] = 0;
2402 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2404 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
2410 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
2411 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2415 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2416 priv->imsg_ring[mbox].buf_base,
2417 priv->imsg_ring[mbox].buf_phys);
2419 priv->imsg_ring[mbox].buf_base = NULL;
2423 priv->imsg_ring[mbox].size * 8,
2424 priv->imsg_ring[mbox].imfq_base,
2425 priv->imsg_ring[mbox].imfq_phys);
2427 priv->imsg_ring[mbox].imfq_base = NULL;
2431 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2432 priv->imsg_ring[mbox].imd_base,
2433 priv->imsg_ring[mbox].imd_phys);
2435 priv->imsg_ring[mbox].imd_base = NULL;
2441 * @mbox: Inbound mailbox number
2446 static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
2452 rx_slot = priv->imsg_ring[mbox].rx_slot;
2453 if (priv->imsg_ring[mbox].imq_base[rx_slot]) {
2461 priv->imsg_ring[mbox].imq_base[rx_slot] = buf;
2463 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
2464 priv->imsg_ring[mbox].rx_slot = 0;
2473 * @mbox: Inbound mailbox number
2477 static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox)
2486 int ch = mbox + 4;
2489 if (!priv->imsg_init[mbox])
2492 desc = priv->imsg_ring[mbox].imd_base;
2493 desc += priv->imsg_ring[mbox].desc_rdptr;
2498 rx_slot = priv->imsg_ring[mbox].rx_slot;
2499 while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) {
2500 if (++rx_slot == priv->imsg_ring[mbox].size)
2507 rx_virt = priv->imsg_ring[mbox].buf_base +
2508 (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys);
2510 buf = priv->imsg_ring[mbox].imq_base[rx_slot];
2516 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2519 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
2520 priv->imsg_ring[mbox].desc_rdptr = 0;
2522 iowrite32(priv->imsg_ring[mbox].desc_rdptr,
2526 free_ptr = priv->imsg_ring[mbox].imfq_base;
2527 free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys);
2529 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
2530 priv->imsg_ring[mbox].fq_wrptr = 0;
2532 iowrite32(priv->imsg_ring[mbox].fq_wrptr,