rapidio/devices/tsi721.c

381 	regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
384 		priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
411 	wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
412 	rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE;
442 				  TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
446 		priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
449 	regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
452 		priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
454 	wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
489 		if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
492 						TSI721_SR_CHINT(IDB_QUEUE));
501 				priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
502 			ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
587 		priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
589 		priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
597 	intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
601 	intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
693 	sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
698 	iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
700 	sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
751 	entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
1407 		priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
1409 		priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
1411 		priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
1413 	iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
1415 	iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
1417 	iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));