drivers/pwm/pwm-tegra.c

84 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
86 	return readl(pc->regs + (offset << 4));
89 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
91 	writel(value, pc->regs + (offset << 4));
97 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
116 	if (period_ns < pc->min_period_ns)
132 	if (pc->soc->num_channels == 1) {
147 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
163 		pc->clk_rate = clk_get_rate(pc->clk);
167 	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
200 	pwm_writel(pc, pwm->hwpwm, val);
213 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
221 	val = pwm_readl(pc, pwm->hwpwm);
223 	pwm_writel(pc, pwm->hwpwm, val);
230 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
233 	val = pwm_readl(pc, pwm->hwpwm);
235 	pwm_writel(pc, pwm->hwpwm, val);
273 	struct tegra_pwm_chip *pc;
279 	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));
282 	pc = to_tegra_pwm_chip(chip);
284 	pc->soc = soc;
286 	pc->regs = devm_platform_ioremap_resource(pdev, 0);
287 	if (IS_ERR(pc->regs))
288 		return PTR_ERR(pc->regs);
292 	pc->clk = devm_clk_get(&pdev->dev, NULL);
293 	if (IS_ERR(pc->clk))
294 		return PTR_ERR(pc->clk);
306 	ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);
317 	pc->clk_rate = clk_get_rate(pc->clk);
320 	pc->min_period_ns =
321 	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
323 	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
324 	if (IS_ERR(pc->rst)) {
325 		ret = PTR_ERR(pc->rst);
330 	reset_control_deassert(pc->rst);
337 		reset_control_assert(pc->rst);
353 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
357 	reset_control_assert(pc->rst);
365 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
368 	clk_disable_unprepare(pc->clk);
372 		clk_prepare_enable(pc->clk);
382 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
389 	err = clk_prepare_enable(pc->clk);