drivers/pwm/pwm-rockchip.c

63 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
64 	u32 enable_conf = pc->data->enable_conf;
70 	ret = clk_enable(pc->pclk);
74 	ret = clk_enable(pc->clk);
78 	clk_rate = clk_get_rate(pc->clk);
80 	tmp = readl_relaxed(pc->base + pc->data->regs.period);
81 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
84 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
85 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
88 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
91 	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
96 	clk_disable(pc->clk);
97 	clk_disable(pc->pclk);
105 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
110 	clk_rate = clk_get_rate(pc->clk);
119 				       pc->data->prescaler * NSEC_PER_SEC);
122 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
128 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
129 	if (pc->data->supports_lock) {
131 		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
134 	writel(period, pc->base + pc->data->regs.period);
135 	writel(duty, pc->base + pc->data->regs.duty);
137 	if (pc->data->supports_polarity) {
150 	if (pc->data->supports_lock)
153 	writel(ctrl, pc->base + pc->data->regs.ctrl);
160 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
161 	u32 enable_conf = pc->data->enable_conf;
166 		ret = clk_enable(pc->clk);
171 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
178 	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
181 		clk_disable(pc->clk);
189 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
194 	ret = clk_enable(pc->pclk);
198 	ret = clk_enable(pc->clk);
206 	    !pc->data->supports_lock) {
221 	clk_disable(pc->clk);
222 	clk_disable(pc->pclk);
299 	struct rockchip_pwm_chip *pc;
304 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pc));
307 	pc = to_rockchip_pwm_chip(chip);
309 	pc->base = devm_platform_ioremap_resource(pdev, 0);
310 	if (IS_ERR(pc->base))
311 		return PTR_ERR(pc->base);
313 	pc->clk = devm_clk_get(&pdev->dev, "pwm");
314 	if (IS_ERR(pc->clk)) {
315 		pc->clk = devm_clk_get(&pdev->dev, NULL);
316 		if (IS_ERR(pc->clk))
317 			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
324 		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
326 		pc->pclk = pc->clk;
328 	if (IS_ERR(pc->pclk))
329 		return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
331 	ret = clk_prepare_enable(pc->clk);
335 	ret = clk_prepare_enable(pc->pclk);
343 	pc->data = device_get_match_data(&pdev->dev);
346 	enable_conf = pc->data->enable_conf;
347 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
358 		clk_disable(pc->clk);
360 	clk_disable(pc->pclk);
365 	clk_disable_unprepare(pc->pclk);
367 	clk_disable_unprepare(pc->clk);
375 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
379 	clk_unprepare(pc->pclk);
380 	clk_unprepare(pc->clk);