Lines Matching refs:period
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
27 * - period for current cycle = current_period + new period
28 * - duty_cycle for current period = current period + new duty_cycle.
78 * Return number of clock cycles in a given period(ins ns).
141 * @period_ns: New period in nano seconds
143 * Return 0 if successfully changed the period/duty_cycle else appropriate
156 dev_dbg(pwmchip_parent(chip), "requested duty cycle: %d ns, period: %d ns\n",
179 * specified period and duty cycle. The load value determines the
180 * period time and the match value determines the duty time.
182 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
198 "period %d ns too short for clock rate %lu Hz\n",
211 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
213 dev_dbg(pwmchip_parent(chip), "using maximum of 1 clock cycle less than period\n");
217 dev_dbg(pwmchip_parent(chip), "effective duty cycle: %lld ns, period: %lld ns\n",
286 state->period);