drivers/pwm/pwm-mtk-disp.c

57 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
60 	void __iomem *address = mdp->base + offset;
72 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
80 	if (!state->enabled && mdp->enabled) {
81 		mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
82 					 mdp->data->enable_mask, 0x0);
83 		clk_disable_unprepare(mdp->clk_mm);
84 		clk_disable_unprepare(mdp->clk_main);
86 		mdp->enabled = false;
90 	if (!mdp->enabled) {
91 		err = clk_prepare_enable(mdp->clk_main);
93 			dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n",
98 		err = clk_prepare_enable(mdp->clk_mm);
100 			dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n",
102 			clk_disable_unprepare(mdp->clk_main);
117 	rate = clk_get_rate(mdp->clk_main);
121 		if (!mdp->enabled) {
122 			clk_disable_unprepare(mdp->clk_mm);
123 			clk_disable_unprepare(mdp->clk_main);
136 	if (mdp->data->bls_debug && !mdp->data->has_commit) {
141 		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
142 					 mdp->data->bls_debug_mask,
143 					 mdp->data->bls_debug_mask);
144 		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
145 					 mdp->data->con0_sel,
146 					 mdp->data->con0_sel);
149 	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
152 	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
156 	if (mdp->data->has_commit) {
157 		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
158 					 mdp->data->commit_mask,
159 					 mdp->data->commit_mask);
160 		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
161 					 mdp->data->commit_mask,
165 	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
166 				 mdp->data->enable_mask);
167 	mdp->enabled = true;
176 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
181 	err = clk_prepare_enable(mdp->clk_main);
183 		dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
187 	err = clk_prepare_enable(mdp->clk_mm);
189 		dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
190 		clk_disable_unprepare(mdp->clk_main);
199 	if (mdp->data->bls_debug)
200 		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
201 					 mdp->data->bls_debug_mask,
202 					 mdp->data->bls_debug_mask);
204 	rate = clk_get_rate(mdp->clk_main);
205 	con0 = readl(mdp->base + mdp->data->con0);
206 	con1 = readl(mdp->base + mdp->data->con1);
207 	pwm_en = readl(mdp->base + DISP_PWM_EN);
208 	state->enabled = !!(pwm_en & mdp->data->enable_mask);
220 	clk_disable_unprepare(mdp->clk_mm);
221 	clk_disable_unprepare(mdp->clk_main);
234 	struct mtk_disp_pwm *mdp;
237 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*mdp));
240 	mdp = to_mtk_disp_pwm(chip);
242 	mdp->data = of_device_get_match_data(&pdev->dev);
244 	mdp->base = devm_platform_ioremap_resource(pdev, 0);
245 	if (IS_ERR(mdp->base))
246 		return PTR_ERR(mdp->base);
248 	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
249 	if (IS_ERR(mdp->clk_main))
250 		return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_main),
253 	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
254 	if (IS_ERR(mdp->clk_mm))
255 		return dev_err_probe(&pdev->dev, PTR_ERR(mdp->clk_mm),