Lines Matching refs:clk
11 #include <linux/clk.h>
29 struct clk *clk[];
52 struct clk *clk;
61 clk = clk_get(pwmchip_parent(chip), name);
62 if (IS_ERR(clk)) {
64 "error %pe: Failed to get clock\n", clk);
65 return PTR_ERR(clk);
68 err = clk_prepare_enable(clk);
70 clk_put(clk);
74 jz->clk[pwm->hwpwm] = clk;
82 struct clk *clk = jz->clk[pwm->hwpwm];
84 clk_disable_unprepare(clk);
85 clk_put(clk);
128 struct clk *clk = jz->clk[pwm->hwpwm];
143 * down, which is not a valid assumption given by the clk API, but only
144 * happens to be true with the clk drivers used for Ingenic SoCs.
146 * Right now, there is no alternative as the clk API does not have a
150 rate = clk_round_rate(clk, tmp);
171 err = clk_set_rate(clk, rate);
234 chip = devm_pwmchip_alloc(dev, info->num_pwms, struct_size(jz, clk, info->num_pwms));