Lines Matching refs:timebase
43 * PWM period is specified with a timebase register,
45 * specified in step periods, in the [0, $timebase] range.
46 * In other words, the timebase imposes the duty cycle
47 * resolution. Therefore, let's constraint the timebase to
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
92 u32 val, div, duty, timebase;
110 timebase = DIV_ROUND_UP(mul, 1);
113 timebase = DIV_ROUND_UP(mul, 8);
116 timebase = DIV_ROUND_UP(mul, 64);
119 timebase = DIV_ROUND_UP(mul, 512);
122 "failed to configure timebase steps/divider value\n");
126 duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
139 (timebase << PWM_CH_CFG_TMBASE_SHIFT);