drivers/pwm/pwm-fsl-ftm.c

60 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
64 	regmap_read(fpc->regmap, FTM_FMS, &val);
66 		regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
69 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
71 	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
89 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
91 	ret = clk_prepare_enable(fpc->ipg_clk);
92 	if (!ret && fpc->soc->has_enable_bits) {
93 		mutex_lock(&fpc->lock);
94 		regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
95 		mutex_unlock(&fpc->lock);
103 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
105 	if (fpc->soc->has_enable_bits) {
106 		mutex_lock(&fpc->lock);
107 		regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
108 		mutex_unlock(&fpc->lock);
111 	clk_disable_unprepare(fpc->ipg_clk);
114 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
120 	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
123 	do_div(exval, rate >> fpc->period.clk_ps);
127 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
136 	c = clk_get_rate(fpc->clk[index]);
154 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
162 	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
167 	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
168 	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
178 	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
182 	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
185 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
190 	unsigned int period = fpc->period.mod_period + 1;
191 	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
199 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
204 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
211 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
216 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
227 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
234 	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
239 	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
247 	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
248 		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
254 		if (fpc->period.clk_select != periodcfg.clk_select) {
256 			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
259 			ret = clk_prepare_enable(fpc->clk[newclk]);
262 			clk_disable_unprepare(fpc->clk[oldclk]);
267 	ftm_clear_write_protection(fpc);
270 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
272 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
274 		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
276 		fpc->period = periodcfg;
279 	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
281 	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
283 	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
289 	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
291 	ftm_set_write_protection(fpc);
299 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
312 	mutex_lock(&fpc->lock);
316 			regmap_set_bits(fpc->regmap, FTM_OUTMASK,
318 			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
319 			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
331 		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
335 		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
337 			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
341 		regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
345 	mutex_unlock(&fpc->lock);
355 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
359 	ret = clk_prepare_enable(fpc->ipg_clk);
363 	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
364 	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
365 	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
367 	clk_disable_unprepare(fpc->ipg_clk);
396 	struct fsl_pwm_chip *fpc;
400 	chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
403 	fpc = to_fsl_chip(chip);
405 	mutex_init(&fpc->lock);
407 	fpc->soc = of_device_get_match_data(&pdev->dev);
413 	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
415 	if (IS_ERR(fpc->regmap)) {
417 		return PTR_ERR(fpc->regmap);
420 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
421 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
423 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
426 	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(&pdev->dev, "ftm_fix");
427 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
428 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
430 	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(&pdev->dev, "ftm_ext");
431 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
432 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
434 	fpc->clk[FSL_PWM_CLK_CNTEN] =
436 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
437 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
443 	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
444 	if (IS_ERR(fpc->ipg_clk))
445 		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
457 	return fsl_pwm_init(fpc);
464 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
467 	regcache_cache_only(fpc->regmap, true);
468 	regcache_mark_dirty(fpc->regmap);
476 		clk_disable_unprepare(fpc->ipg_clk);
481 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
482 		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
491 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
500 		clk_prepare_enable(fpc->ipg_clk);
505 		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
506 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
510 	regcache_cache_only(fpc->regmap, false);
511 	regcache_sync(fpc->regmap);