Lines Matching refs:pc
39 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
42 value = readl(pc->base + PWM_CONTROL);
45 writel(value, pc->base + PWM_CONTROL);
52 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
55 value = readl(pc->base + PWM_CONTROL);
57 writel(value, pc->base + PWM_CONTROL);
64 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
84 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
90 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
99 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
100 writel(val, pc->base + DUTY(pwm->hwpwm));
103 val = readl(pc->base + PWM_CONTROL);
116 writel(val, pc->base + PWM_CONTROL);
137 struct bcm2835_pwm *pc;
140 chip = devm_pwmchip_alloc(&pdev->dev, 2, sizeof(*pc));
143 pc = to_bcm2835_pwm(chip);
145 pc->base = devm_platform_ioremap_resource(pdev, 0);
146 if (IS_ERR(pc->base))
147 return PTR_ERR(pc->base);
149 pc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
150 if (IS_ERR(pc->clk))
151 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
154 ret = clk_rate_exclusive_get(pc->clk);
160 pc->clk);
164 pc->rate = clk_get_rate(pc->clk);
165 if (!pc->rate)
172 platform_set_drvdata(pdev, pc);
184 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
186 clk_disable_unprepare(pc->clk);
193 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
195 return clk_prepare_enable(pc->clk);