drivers/pwm/pwm-atmel.c

196 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
209 	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
241 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
244 	if (atmel_pwm->data->regs.duty_upd ==
245 	    atmel_pwm->data->regs.period_upd) {
246 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
248 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
251 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
252 			    atmel_pwm->data->regs.duty_upd, cdty);
253 	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
260 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
262 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
263 			    atmel_pwm->data->regs.duty, cdty);
264 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
265 			    atmel_pwm->data->regs.period, cprd);
271 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
274 	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
276 	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
284 	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
289 		clk_disable(atmel_pwm->clk);
295 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
301 		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
306 			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
308 			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
309 						  atmel_pwm->data->regs.period);
330 			ret = clk_enable(atmel_pwm->clk);
338 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
344 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
346 		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
357 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
360 	sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
361 	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
364 		unsigned long rate = clk_get_rate(atmel_pwm->clk);
370 		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
371 					  atmel_pwm->data->regs.period);
377 		atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
379 		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
380 					  atmel_pwm->data->regs.duty);
463 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
468 	sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
478 		ret = clk_enable(atmel_pwm->clk);
493 		clk_disable(atmel_pwm->clk);
500 	struct atmel_pwm_chip *atmel_pwm;
504 	chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*atmel_pwm));
508 	atmel_pwm = to_atmel_pwm_chip(chip);
509 	atmel_pwm->data = of_device_get_match_data(&pdev->dev);
511 	atmel_pwm->update_pending = 0;
512 	spin_lock_init(&atmel_pwm->lock);
514 	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
515 	if (IS_ERR(atmel_pwm->base))
516 		return PTR_ERR(atmel_pwm->base);
518 	atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
519 	if (IS_ERR(atmel_pwm->clk))
520 		return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),