Lines Matching refs:bc
45 void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
46 void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
67 struct imx8mp_blk_ctrl *bc;
74 int (*probe) (struct imx8mp_blk_ctrl *bc);
76 void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
77 void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
147 static int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc)
154 clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL);
163 clk_hsio_pll->regmap = bc->regmap;
167 ret = devm_clk_hw_register(bc->bus_power_dev, hw);
171 return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw);
174 static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
179 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
182 regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
185 regmap_set_bits(bc->regmap, GPR_REG0,
193 static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
198 regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
201 regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
204 regmap_clear_bits(bc->regmap, GPR_REG0,
215 struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
217 struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks;
218 int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks;
230 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
234 regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
243 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
305 static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
310 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
311 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
314 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
317 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
318 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
320 regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0,
324 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
325 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
328 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
329 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
332 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
333 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
336 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
338 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
341 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
343 regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
346 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
347 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
348 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
349 regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
352 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
355 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
356 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
363 static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
368 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
369 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
372 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
374 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
375 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
380 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
381 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
384 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
385 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
388 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
389 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
392 regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
393 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
395 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
398 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
402 regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
403 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
404 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
405 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
408 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
411 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
412 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
422 struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
434 regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
435 regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
436 regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
437 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
439 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
527 struct imx8mp_blk_ctrl *bc = domain->bc;
531 ret = pm_runtime_resume_and_get(bc->bus_power_dev);
533 dev_err(bc->dev, "failed to power up bus domain\n");
540 dev_err(bc->dev, "failed to enable clocks\n");
545 bc->power_on(bc, domain);
550 dev_err(bc->dev, "failed to power up peripheral domain\n");
556 dev_err(bc->dev, "failed to set icc bw\n");
565 pm_runtime_put(bc->bus_power_dev);
574 struct imx8mp_blk_ctrl *bc = domain->bc;
579 dev_err(bc->dev, "failed to enable clocks\n");
584 bc->power_off(bc, domain);
592 pm_runtime_put(bc->bus_power_dev);
603 struct imx8mp_blk_ctrl *bc;
613 bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
614 if (!bc)
617 bc->dev = dev;
627 bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
628 if (IS_ERR(bc->regmap))
629 return dev_err_probe(dev, PTR_ERR(bc->regmap),
632 bc->domains = devm_kcalloc(dev, num_domains,
635 if (!bc->domains)
638 bc->onecell_data.num_domains = num_domains;
639 bc->onecell_data.domains =
642 if (!bc->onecell_data.domains)
645 bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus");
646 if (IS_ERR(bc->bus_power_dev))
647 return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
650 bc->power_off = bc_data->power_off;
651 bc->power_on = bc_data->power_on;
655 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
704 domain->bc = bc;
727 bc->onecell_data.domains[i] = &domain->genpd;
730 ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
736 bc->power_nb.notifier_call = bc_data->power_notifier_fn;
737 ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
744 ret = bc_data->probe(bc);
749 dev_set_drvdata(dev, bc);
757 pm_genpd_remove(&bc->domains[i].genpd);
758 dev_pm_domain_detach(bc->domains[i].power_dev, true);
761 dev_pm_domain_detach(bc->bus_power_dev, true);
768 struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
773 for (i = 0; bc->onecell_data.num_domains; i++) {
774 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
780 dev_pm_genpd_remove_notifier(bc->bus_power_dev);
782 dev_pm_domain_detach(bc->bus_power_dev, true);
788 struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
799 ret = pm_runtime_get_sync(bc->bus_power_dev);
801 pm_runtime_put_noidle(bc->bus_power_dev);
805 for (i = 0; i < bc->onecell_data.num_domains; i++) {
806 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
819 pm_runtime_put(bc->domains[i].power_dev);
821 pm_runtime_put(bc->bus_power_dev);
828 struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
831 for (i = 0; i < bc->onecell_data.num_domains; i++)
832 pm_runtime_put(bc->domains[i].power_dev);
834 pm_runtime_put(bc->bus_power_dev);