Lines Matching refs:HDMI_RTX_CLK_CTL1
298 #define HDMI_RTX_CLK_CTL1 0x50
317 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
324 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
328 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
332 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
338 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
347 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
355 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
374 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
381 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
385 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
389 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
395 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
405 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
412 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
436 regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);