platform/x86/pmc_atom.c

15 #include <linux/platform_data/x86/clk-pmc-atom.h>
206 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
208 	return readl(pmc->regmap + reg_offset);
211 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
213 	writel(val, pmc->regmap + reg_offset);
218 	struct pmc_dev *pmc = &pmc_device;
220 	if (!pmc->init)
223 	*value = pmc_reg_read(pmc, offset);
244 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
254 	pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
275 	struct pmc_dev *pmc = s->private;
276 	const struct pmc_reg_map *m = pmc->map;
280 	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
281 	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
282 	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
283 	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
298 	struct pmc_dev *pmc = s->private;
299 	const struct pmc_bit_map *map = pmc->map->pss;
300 	u32 pss = pmc_reg_read(pmc, PMC_PSS);
315 	struct pmc_dev *pmc = s->private;
318 	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
319 	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
320 	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
321 	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
322 	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
334 static void pmc_dbgfs_register(struct pmc_dev *pmc)
340 	pmc->dbgfs_dir = dir;
342 	debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
344 	debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
346 	debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
350 static void pmc_dbgfs_register(struct pmc_dev *pmc)
440 	clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
475 	struct pmc_dev *pmc = &pmc_device;
476 	const struct pmc_reg_map *m = pmc->map;
482 	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
483 	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
484 	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
485 	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
508 		u32 ctl = pmc_reg_read(pmc, PMC_CLK_CTL_OFFSET + 4 * i);
531 	struct pmc_dev *pmc = &pmc_device;
544 	pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
545 	pmc->base_addr &= PMC_BASE_ADDR_MASK;
547 	pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN);
548 	if (!pmc->regmap) {
553 	pmc->map = map;
556 	pmc_hw_reg_setup(pmc);
558 	pmc_dbgfs_register(pmc);
561 	ret = pmc_setup_clks(pdev, pmc->regmap, data);
567 	pmc->init = true;