intel/pmc/core.c

58 static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset)
60 	return readl(pmc->regbase + reg_offset);
63 static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset,
66 	writel(val, pmc->regbase + reg_offset);
69 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc *pmc, u32 value)
77 	const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
79 	if (pmc->map == &adl_reg_map)
82 		return (u64)value * pmc->map->slp_s0_res_counter_step;
87 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
88 	const struct pmc_reg_map *map = pmc->map;
98 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
106 	pmc_core_reg_write(pmc, map->etr3_offset, reg);
108 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
126 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
127 	const struct pmc_reg_map *map = pmc->map;
131 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
141 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
142 	const struct pmc_reg_map *map = pmc->map;
150 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
199 	struct pmc *pmc = data;
200 	const struct pmc_reg_map *map = pmc->map;
203 	value = pmc_core_reg_read(pmc, map->slp_s0_offset);
204 	*val = pmc_core_adjust_slp_s0_step(pmc, value);
213 	struct pmc *pmc = data;
214 	const struct pmc_reg_map *map = pmc->map;
217 	value = pmc_core_reg_read(pmc, map->pson_residency_offset);
225 static int pmc_core_check_read_lock_bit(struct pmc *pmc)
229 	value = pmc_core_reg_read(pmc, pmc->map->pm_cfg_offset);
230 	return value & BIT(pmc->map->pm_read_disable_bit);
233 static void pmc_core_slps0_display(struct pmc *pmc, struct device *dev,
236 	const struct pmc_bit_map **maps = pmc->map->slps0_dbg_maps;
238 	int offset = pmc->map->slps0_dbg_offset;
243 		data = pmc_core_reg_read(pmc, offset);
270 static void pmc_core_lpm_display(struct pmc *pmc, struct device *dev,
284 		lpm_regs[index] = pmc_core_reg_read(pmc, offset);
313 static inline u8 pmc_core_reg_read_byte(struct pmc *pmc, int offset)
315 	return readb(pmc->regbase + offset);
332 		struct pmc *pmc = pmcdev->pmcs[i];
337 		if (!pmc)
340 		maps = pmc->map->pfear_sts;
341 		iter = pmc->map->ppfear0_offset;
343 		for (index = 0; index < pmc->map->ppfear_buckets &&
345 			pf_regs[index] = pmc_core_reg_read_byte(pmc, iter);
349 			     index < pmc->map->ppfear_buckets * 8; ip++, index++)
360 static int pmc_core_mtpmc_link_status(struct pmc *pmc)
364 	value = pmc_core_reg_read(pmc, SPT_PMC_PM_STS_OFFSET);
368 static int pmc_core_send_msg(struct pmc *pmc, u32 *addr_xram)
374 		if (pmc_core_mtpmc_link_status(pmc) == 0)
379 	if (timeout <= 0 && pmc_core_mtpmc_link_status(pmc))
383 	pmc_core_reg_write(pmc, SPT_PMC_MTPMC_OFFSET, dest);
390 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
391 	const struct pmc_bit_map *map = pmc->map->mphy_sts;
406 	if (pmc_core_send_msg(pmc, &mphy_core_reg_low) != 0) {
412 	val_low = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
414 	if (pmc_core_send_msg(pmc, &mphy_core_reg_high) != 0) {
420 	val_high = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
445 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
446 	const struct pmc_bit_map *map = pmc->map->pll_sts;
458 	if (pmc_core_send_msg(pmc, &mphy_common_reg) != 0) {
465 	val = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET);
481 	struct pmc *pmc;
489 	 * pmc index and ltr index needs to be calculated from it.
492 		pmc = pmcdev->pmcs[pmc_index];
494 		if (!pmc)
497 		map = pmc->map;
504 		 * ltr index from zero for next pmc, subtract it by 1.
512 	pr_debug("ltr_ignore for pmc%d: ltr_index:%d\n", pmc_index, ltr_index);
516 	reg = pmc_core_reg_read(pmc, map->ltr_ignore_offset);
521 	pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg);
568 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
569 	const struct pmc_reg_map *map = pmc->map;
577 	fd = pmc_core_reg_read(pmc, map->slps0_dbg_offset);
582 	pmc_core_reg_write(pmc, map->slps0_dbg_offset, fd);
645 		struct pmc *pmc = pmcdev->pmcs[i];
648 		if (!pmc)
651 		map = pmc->map->ltr_show_sts;
654 			ltr_raw_data = pmc_core_reg_read(pmc,
681 static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset,
684 	u64 lpm_res = pmc_core_reg_read(pmc, offset);
692 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
693 	const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
694 	u32 offset = pmc->map->lpm_residency_offset;
701 			   adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2));
714 		struct pmc *pmc = pmcdev->pmcs[i];
718 		if (!pmc)
720 		maps = pmc->map->lpm_sts;
721 		offset = pmc->map->lpm_status_offset;
722 		pmc_core_lpm_display(pmc, NULL, s, offset, i, "STATUS", maps);
735 		struct pmc *pmc = pmcdev->pmcs[i];
739 		if (!pmc)
741 		maps = pmc->map->lpm_sts;
742 		offset = pmc->map->lpm_live_status_offset;
743 		pmc_core_lpm_display(pmc, NULL, s, offset, i, "LIVE_STATUS", maps);
770 		struct pmc *pmc = pmcdev->pmcs[pmc_index];
773 		if (!pmc)
776 		maps = pmc->map->lpm_sts;
777 		num_maps = pmc->map->lpm_num_maps;
778 		sts_offset = pmc->map->lpm_status_offset;
779 		lpm_req_regs = pmc->lpm_req_regs;
808 			lpm_status = pmc_core_reg_read(pmc, sts_offset + (mp * 4));
824 				seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name);
888 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
893 	reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
920 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
957 		reg = pmc_core_reg_read(pmc, pmc->map->etr3_offset);
959 		pmc_core_reg_write(pmc, pmc->map->etr3_offset, reg);
969 		reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
971 		pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
984 	pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
993 	struct pmc *pmc = s->private;
994 	const struct pmc_bit_map *map = pmc->map->msr_sts;
1044 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1052 	if (!pmc->map->lpm_num_maps)
1055 	lpm_en = pmc_core_reg_read(pmc, pmc->map->lpm_en_offset);
1063 	lpm_pri = pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset);
1093 int get_primary_reg_base(struct pmc *pmc)
1098 		pmc->base_addr = PMC_BASE_ADDR_DEFAULT;
1100 		if (page_is_ram(PHYS_PFN(pmc->base_addr)))
1103 		pmc->base_addr = slp_s0_addr - pmc->map->slp_s0_offset;
1106 	pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
1107 	if (!pmc->regbase)
1182 	struct pmc *primary_pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1303 static void pmc_core_xtal_ignore(struct pmc *pmc)
1307 	value = pmc_core_reg_read(pmc, pmc->map->pm_vric1_offset);
1312 	pmc_core_reg_write(pmc, pmc->map->pm_vric1_offset, value);
1327 static void pmc_core_do_dmi_quirks(struct pmc *pmc)
1332 		pmc_core_xtal_ignore(pmc);
1341 		struct pmc *pmc = pmcdev->pmcs[i];
1343 		if (pmc)
1344 			iounmap(pmc->regbase);
1365 	struct pmc *primary_pmc;
1443 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1460 	if (pmc_core_dev_state_get(pmc, &pmcdev->s0ix_counter))
1498 	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
1499 	const struct pmc_bit_map **maps = pmc->map->lpm_sts;
1500 	int offset = pmc->map->lpm_status_offset;
1536 	if (pmc->map->slps0_dbg_maps)
1537 		pmc_core_slps0_display(pmc, dev, NULL);
1540 		struct pmc *pmc = pmcdev->pmcs[i];
1542 		if (!pmc)
1544 		if (pmc->map->lpm_sts)
1545 			pmc_core_lpm_display(pmc, dev, NULL, offset, i, "STATUS", maps);