intel/pmc/core.c

77 	const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
79 	if (pmc->map == &adl_reg_map)
82 		return (u64)value * pmc->map->slp_s0_res_counter_step;
88 	const struct pmc_reg_map *map = pmc->map;
92 	if (!map->etr3_offset)
98 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
106 	pmc_core_reg_write(pmc, map->etr3_offset, reg);
108 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
127 	const struct pmc_reg_map *map = pmc->map;
131 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
142 	const struct pmc_reg_map *map = pmc->map;
145 	if (!map->etr3_offset)
150 	reg = pmc_core_reg_read(pmc, map->etr3_offset);
200 	const struct pmc_reg_map *map = pmc->map;
203 	value = pmc_core_reg_read(pmc, map->slp_s0_offset);
214 	const struct pmc_reg_map *map = pmc->map;
217 	value = pmc_core_reg_read(pmc, map->pson_residency_offset);
218 	*val = (u64)value * map->pson_residency_counter_step;
229 	value = pmc_core_reg_read(pmc, pmc->map->pm_cfg_offset);
230 	return value & BIT(pmc->map->pm_read_disable_bit);
236 	const struct pmc_bit_map **maps = pmc->map->slps0_dbg_maps;
237 	const struct pmc_bit_map *map;
238 	int offset = pmc->map->slps0_dbg_offset;
242 		map = *maps;
245 		while (map->name) {
248 					map->name,
249 					data & map->bit_mask ? "Yes" : "No");
252 					   map->name,
253 					   data & map->bit_mask ? "Yes" : "No");
254 			++map;
340 		maps = pmc->map->pfear_sts;
341 		iter = pmc->map->ppfear0_offset;
343 		for (index = 0; index < pmc->map->ppfear_buckets &&
349 			     index < pmc->map->ppfear_buckets * 8; ip++, index++)
391 	const struct pmc_bit_map *map = pmc->map->mphy_sts;
422 	for (index = 0; index < 8 && map[index].name; index++) {
424 			   map[index].name,
425 			   map[index].bit_mask & val_low ? "Not power gated" :
429 	for (index = 8; map[index].name; index++) {
431 			   map[index].name,
432 			   map[index].bit_mask & val_high ? "Not power gated" :
446 	const struct pmc_bit_map *map = pmc->map->pll_sts;
467 	for (index = 0; map[index].name ; index++) {
469 			   map[index].name,
470 			   map[index].bit_mask & val ? "Active" : "Idle");
482 	const struct pmc_reg_map *map;
497 		map = pmc->map;
498 		if (ltr_index <= map->ltr_ignore_max)
501 		/* Along with IP names, ltr_show map includes CURRENT_PLATFORM
506 		ltr_index = ltr_index - (map->ltr_ignore_max + 2) - 1;
516 	reg = pmc_core_reg_read(pmc, map->ltr_ignore_offset);
521 	pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg);
569 	const struct pmc_reg_map *map = pmc->map;
577 	fd = pmc_core_reg_read(pmc, map->slps0_dbg_offset);
582 	pmc_core_reg_write(pmc, map->slps0_dbg_offset, fd);
646 		const struct pmc_bit_map *map;
651 		map = pmc->map->ltr_show_sts;
652 		for (index = 0; map[index].name; index++) {
655 							 map[index].bit_mask);
671 				   ltr_index, i, map[index].name, ltr_raw_data,
693 	const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2;
694 	u32 offset = pmc->map->lpm_residency_offset;
720 		maps = pmc->map->lpm_sts;
721 		offset = pmc->map->lpm_status_offset;
741 		maps = pmc->map->lpm_sts;
742 		offset = pmc->map->lpm_live_status_offset;
776 		maps = pmc->map->lpm_sts;
777 		num_maps = pmc->map->lpm_num_maps;
778 		sts_offset = pmc->map->lpm_status_offset;
796 			const struct pmc_bit_map *map;
807 			/* Get the last latched status for this map */
810 			/*  Loop over elements in this map */
811 			map = maps[mp];
812 			for (i = 0; map[i].name && i < len; i++) {
813 				u32 bit_mask = map[i].bit_mask;
824 				seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name);
893 	reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
957 		reg = pmc_core_reg_read(pmc, pmc->map->etr3_offset);
959 		pmc_core_reg_write(pmc, pmc->map->etr3_offset, reg);
969 		reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset);
971 		pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
984 	pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg);
994 	const struct pmc_bit_map *map = pmc->map->msr_sts;
998 	for (index = 0; map[index].name ; index++) {
999 		if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
1004 		seq_printf(s, "%-8s : %llu\n", map[index].name,
1052 	if (!pmc->map->lpm_num_maps)
1055 	lpm_en = pmc_core_reg_read(pmc, pmc->map->lpm_en_offset);
1063 	lpm_pri = pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset);
1103 		pmc->base_addr = slp_s0_addr - pmc->map->slp_s0_offset;
1106 	pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
1191 	if (primary_pmc->map->pfear_sts)
1203 	if (primary_pmc->map->pll_sts)
1207 	if (primary_pmc->map->mphy_sts)
1212 	if (primary_pmc->map->slps0_dbg_maps) {
1221 	if (primary_pmc->map->lpm_en_offset) {
1227 	if (primary_pmc->map->lpm_status_offset) {
1245 	if (primary_pmc->map->pson_residency_offset && pmc_core_is_pson_residency_enabled(pmcdev)) {
1307 	value = pmc_core_reg_read(pmc, pmc->map->pm_vric1_offset);
1312 	pmc_core_reg_write(pmc, pmc->map->pm_vric1_offset, value);
1499 	const struct pmc_bit_map **maps = pmc->map->lpm_sts;
1500 	int offset = pmc->map->lpm_status_offset;
1536 	if (pmc->map->slps0_dbg_maps)
1544 		if (pmc->map->lpm_sts)