platform/mellanox/mlxbf-tmfifo.c

76  * @fifo: pointer to the tmfifo structure
95 	struct mlxbf_tmfifo *fifo;
150  * @fifo: pointer to the tmfifo structure
155 	struct mlxbf_tmfifo *fifo;
246 static void mlxbf_tmfifo_free_vrings(struct mlxbf_tmfifo *fifo,
268 static int mlxbf_tmfifo_alloc_vrings(struct mlxbf_tmfifo *fifo,
279 		vring->fifo = fifo;
290 			mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
303 static void mlxbf_tmfifo_disable_irqs(struct mlxbf_tmfifo *fifo)
308 		irq = fifo->irq_info[i].irq;
309 		fifo->irq_info[i].irq = 0;
319 	if (!test_and_set_bit(irq_info->index, &irq_info->fifo->pend_events))
320 		schedule_work(&irq_info->fifo->work);
440 	struct mlxbf_tmfifo *fifo = container_of(t, struct mlxbf_tmfifo, timer);
443 	rx = !test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events);
444 	tx = !test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
447 		schedule_work(&fifo->work);
449 	mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
510 static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
514 	sts = readq(fifo->rx.sts);
519 static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
527 		tx_reserve = fifo->tx_fifo_size / MLXBF_TMFIFO_RESERVE_RATIO;
531 	sts = readq(fifo->tx.sts);
533 	return fifo->tx_fifo_size - tx_reserve - count;
537 static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
550 	cons = fifo->vdev[VIRTIO_ID_CONSOLE];
567 	writeq(*(u64 *)&hdr, fifo->tx.data);
570 	spin_lock_irqsave(&fifo->spin_lock[0], flags);
584 		writeq(data, fifo->tx.data);
597 	spin_unlock_irqrestore(&fifo->spin_lock[0], flags);
606 	struct mlxbf_tmfifo *fifo = vring->fifo;
615 		data = readq(fifo->rx.data);
644 		writeq(data, fifo->tx.data);
658 	struct mlxbf_tmfifo *fifo = vring->fifo;
667 		*(u64 *)&hdr = readq(fifo->rx.data);
677 			config = &fifo->vdev[vdev_id]->config.net;
694 			struct mlxbf_tmfifo_vdev *tm_dev2 = fifo->vdev[vdev_id];
720 		writeq(*(u64 *)&hdr, fifo->tx.data);
725 	fifo->vring[is_rx] = vring;
737 	struct mlxbf_tmfifo *fifo = vring->fifo;
744 	vdev = &fifo->vdev[vring->vdev_id]->vdev;
800 		fifo->vring[is_rx] = NULL;
817 		spin_lock_irqsave(&fifo->spin_lock[is_rx], flags);
819 		spin_unlock_irqrestore(&fifo->spin_lock[is_rx], flags);
859 	vring->fifo->vring[0] = NULL;
868 	spin_lock_irqsave(&vring->fifo->spin_lock[0], flags);
870 	spin_unlock_irqrestore(&vring->fifo->spin_lock[0], flags);
877 	struct mlxbf_tmfifo *fifo;
880 	fifo = vring->fifo;
883 	if (!fifo || !fifo->vdev[devid])
887 	if (fifo->vring[is_rx] && fifo->vring[is_rx] != vring)
899 				avail = mlxbf_tmfifo_get_rx_avail(fifo);
901 				avail = mlxbf_tmfifo_get_tx_avail(fifo, devid);
910 				writeq(0, vring->fifo->tx.data);
919 			mlxbf_tmfifo_console_tx(fifo, avail);
933 static void mlxbf_tmfifo_work_rxtx(struct mlxbf_tmfifo *fifo, int queue_id,
940 	if (!test_and_clear_bit(irq_id, &fifo->pend_events) ||
941 	    !fifo->irq_info[irq_id].irq)
945 		tm_vdev = fifo->vdev[i];
957 	struct mlxbf_tmfifo *fifo;
959 	fifo = container_of(work, struct mlxbf_tmfifo, work);
960 	if (!fifo->is_ready)
963 	mutex_lock(&fifo->lock);
966 	mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_TX,
970 	mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_RX,
973 	mutex_unlock(&fifo->lock);
981 	struct mlxbf_tmfifo *fifo;
984 	fifo = vring->fifo;
998 			spin_lock_irqsave(&fifo->spin_lock[0], flags);
999 			tm_vdev = fifo->vdev[VIRTIO_ID_CONSOLE];
1001 			spin_unlock_irqrestore(&fifo->spin_lock[0], flags);
1002 			set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
1004 					    &fifo->pend_events)) {
1008 		if (test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events))
1012 	schedule_work(&fifo->work);
1189 				    struct mlxbf_tmfifo *fifo,
1196 	mutex_lock(&fifo->lock);
1198 	tm_vdev = fifo->vdev[vdev_id];
1219 	if (mlxbf_tmfifo_alloc_vrings(fifo, tm_vdev)) {
1230 	fifo->vdev[vdev_id] = tm_vdev;
1240 	mutex_unlock(&fifo->lock);
1244 	mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
1245 	fifo->vdev[vdev_id] = NULL;
1251 	mutex_unlock(&fifo->lock);
1256 static int mlxbf_tmfifo_delete_vdev(struct mlxbf_tmfifo *fifo, int vdev_id)
1260 	mutex_lock(&fifo->lock);
1263 	tm_vdev = fifo->vdev[vdev_id];
1266 		mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
1267 		fifo->vdev[vdev_id] = NULL;
1270 	mutex_unlock(&fifo->lock);
1291 static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
1296 	ctl = readq(fifo->tx.ctl);
1297 	fifo->tx_fifo_size =
1301 			   fifo->tx_fifo_size / 2);
1304 			   fifo->tx_fifo_size - 1);
1305 	writeq(ctl, fifo->tx.ctl);
1308 	ctl = readq(fifo->rx.ctl);
1309 	fifo->rx_fifo_size =
1315 	writeq(ctl, fifo->rx.ctl);
1318 static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
1322 	fifo->is_ready = false;
1323 	del_timer_sync(&fifo->timer);
1324 	mlxbf_tmfifo_disable_irqs(fifo);
1325 	cancel_work_sync(&fifo->work);
1327 		mlxbf_tmfifo_delete_vdev(fifo, i);
1335 	struct mlxbf_tmfifo *fifo;
1345 	fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
1346 	if (!fifo)
1349 	spin_lock_init(&fifo->spin_lock[0]);
1350 	spin_lock_init(&fifo->spin_lock[1]);
1351 	INIT_WORK(&fifo->work, mlxbf_tmfifo_work_handler);
1352 	mutex_init(&fifo->lock);
1355 	fifo->res0 = devm_platform_ioremap_resource(pdev, 0);
1356 	if (IS_ERR(fifo->res0))
1357 		return PTR_ERR(fifo->res0);
1360 	fifo->res1 = devm_platform_ioremap_resource(pdev, 1);
1361 	if (IS_ERR(fifo->res1))
1362 		return PTR_ERR(fifo->res1);
1365 		fifo->rx.ctl = fifo->res1 + MLXBF_TMFIFO_RX_CTL_BF3;
1366 		fifo->rx.sts = fifo->res1 + MLXBF_TMFIFO_RX_STS_BF3;
1367 		fifo->rx.data = fifo->res0 + MLXBF_TMFIFO_RX_DATA_BF3;
1368 		fifo->tx.ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL_BF3;
1369 		fifo->tx.sts = fifo->res1 + MLXBF_TMFIFO_TX_STS_BF3;
1370 		fifo->tx.data = fifo->res0 + MLXBF_TMFIFO_TX_DATA_BF3;
1372 		fifo->rx.ctl = fifo->res0 + MLXBF_TMFIFO_RX_CTL;
1373 		fifo->rx.sts = fifo->res0 + MLXBF_TMFIFO_RX_STS;
1374 		fifo->rx.data = fifo->res0 + MLXBF_TMFIFO_RX_DATA;
1375 		fifo->tx.ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL;
1376 		fifo->tx.sts = fifo->res1 + MLXBF_TMFIFO_TX_STS;
1377 		fifo->tx.data = fifo->res1 + MLXBF_TMFIFO_TX_DATA;
1380 	platform_set_drvdata(pdev, fifo);
1382 	timer_setup(&fifo->timer, mlxbf_tmfifo_timer, 0);
1385 		fifo->irq_info[i].index = i;
1386 		fifo->irq_info[i].fifo = fifo;
1387 		fifo->irq_info[i].irq = platform_get_irq(pdev, i);
1388 		rc = devm_request_irq(dev, fifo->irq_info[i].irq,
1390 				      "tmfifo", &fifo->irq_info[i]);
1393 			fifo->irq_info[i].irq = 0;
1398 	mlxbf_tmfifo_set_threshold(fifo);
1401 	rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_CONSOLE, 0, NULL, 0);
1414 	rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_NET,
1420 	mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
1425 	fifo->is_ready = true;
1429 	mlxbf_tmfifo_cleanup(fifo);
1436 	struct mlxbf_tmfifo *fifo = platform_get_drvdata(pdev);
1438 	mlxbf_tmfifo_cleanup(fifo);