pinctrl/visconti/pinctrl-common.c

41 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
42 	const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin];
49 	dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name);
51 	spin_lock_irqsave(&priv->lock, flags);
64 			val = readl(priv->base + pin->pudsel_offset);
67 			writel(val, priv->base + pin->pudsel_offset);
72 			val = readl(priv->base + pin->pude_offset);
75 			writel(val, priv->base + pin->pude_offset);
76 			dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n",
82 			dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg);
106 			val = readl(priv->base + pin->dsel_offset);
109 			writel(val, priv->base + pin->dsel_offset);
118 	spin_unlock_irqrestore(&priv->lock, flags);
127 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
132 	pins = priv->devdata->groups[selector].pins;
133 	num_pins = priv->devdata->groups[selector].nr_pins;
135 	dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n",
157 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
159 	return priv->devdata->nr_groups;
165 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
167 	return priv->devdata->groups[selector].name;
175 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
177 	*pins = priv->devdata->groups[selector].pins;
178 	*num_pins = priv->devdata->groups[selector].nr_pins;
194 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
196 	return priv->devdata->nr_functions;
202 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
204 	return priv->devdata->functions[selector].name;
212 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
214 	*groups = priv->devdata->functions[selector].groups;
215 	*num_groups = priv->devdata->functions[selector].nr_groups;
223 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
224 	const struct visconti_pin_function *func = &priv->devdata->functions[function];
225 	const struct visconti_pin_group *grp = &priv->devdata->groups[group];
230 	dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__,
233 	spin_lock_irqsave(&priv->lock, flags);
236 	val = readl(priv->base + mux->offset);
239 	writel(val, priv->base + mux->offset);
241 	spin_unlock_irqrestore(&priv->lock, flags);
243 	dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val);
252 	struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
253 	const struct visconti_mux *gpio_mux = &priv->devdata->gpio_mux[pin];
257 	dev_dbg(priv->dev, "%s: pin = %d\n", __func__, pin);
260 	spin_lock_irqsave(&priv->lock, flags);
261 	val = readl(priv->base + gpio_mux->offset);
264 	writel(val, priv->base + gpio_mux->offset);
265 	spin_unlock_irqrestore(&priv->lock, flags);
283 	struct visconti_pinctrl *priv;
287 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
288 	if (!priv)
291 	priv->dev = dev;
292 	priv->devdata = devdata;
293 	spin_lock_init(&priv->lock);
295 	priv->base = devm_platform_ioremap_resource(pdev, 0);
296 	if (IS_ERR(priv->base)) {
298 		return PTR_ERR(priv->base);
309 	priv->pctl_desc.name = dev_name(dev);
310 	priv->pctl_desc.owner = THIS_MODULE;
311 	priv->pctl_desc.pins = pins;
312 	priv->pctl_desc.npins = devdata->nr_pins;
313 	priv->pctl_desc.confops = &visconti_pinconf_ops;
314 	priv->pctl_desc.pctlops = &visconti_pinctrl_ops;
315 	priv->pctl_desc.pmxops = &visconti_pinmux_ops;
317 	ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc,
318 					     priv, &priv->pctl);
325 		devdata->unlock(priv->base);
327 	return pinctrl_enable(priv->pctl);