Lines Matching refs:pctl
61 static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
67 *reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +
73 static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
79 *reg = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +
85 static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
89 u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
91 *reg = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +
94 *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift;
97 static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
103 *reg = bank * pctl->bank_mem_size + pctl->pull_regs_offset +
110 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
114 for (i = 0; i < pctl->ngroups; i++) {
115 struct sunxi_pinctrl_group *grp = pctl->groups + i;
125 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
128 struct sunxi_pinctrl_function *func = pctl->functions;
131 for (i = 0; i < pctl->nfunctions; i++) {
143 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
149 for (i = 0; i < pctl->desc->npins; i++) {
150 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
158 func->variant & pctl->variant))
170 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
176 for (i = 0; i < pctl->desc->npins; i++) {
177 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
196 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
198 return pctl->ngroups;
204 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
206 return pctl->groups[group].name;
214 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
216 *pins = (unsigned *)&pctl->groups[group].pin;
392 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
404 dev_err(pctl->dev, "missing function property in node %pOFn\n",
411 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
436 sunxi_pinctrl_find_group_by_name(pctl, group);
439 dev_err(pctl->dev, "unknown pin %s", group);
443 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
446 dev_err(pctl->dev, "unsupported function %s on pin %s",
514 static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
520 sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
526 sunxi_pull_reg(pctl, pin, reg, shift, mask);
539 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
545 pin -= pctl->desc->pin_base;
547 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
551 val = (readl(pctl->membase + reg) & mask) >> shift;
591 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
592 struct sunxi_pinctrl_group *g = &pctl->groups[group];
601 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
604 pin -= pctl->desc->pin_base;
615 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
651 raw_spin_lock_irqsave(&pctl->lock, flags);
652 writel((readl(pctl->membase + reg) & ~mask) | val << shift,
653 pctl->membase + reg);
654 raw_spin_unlock_irqrestore(&pctl->lock, flags);
663 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
664 struct sunxi_pinctrl_group *g = &pctl->groups[group];
678 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
687 if (!pctl->desc->io_bias_cfg_variant)
698 pin -= pctl->desc->pin_base;
701 switch (pctl->desc->io_bias_cfg_variant) {
718 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
720 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
725 raw_spin_lock_irqsave(&pctl->lock, flags);
726 reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
728 writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
729 raw_spin_unlock_irqrestore(&pctl->lock, flags);
735 raw_spin_lock_irqsave(&pctl->lock, flags);
736 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
738 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
739 raw_spin_unlock_irqrestore(&pctl->lock, flags);
748 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
750 return pctl->nfunctions;
756 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
758 return pctl->functions[function].name;
766 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
768 *groups = pctl->functions[function].groups;
769 *num_groups = pctl->functions[function].ngroups;
778 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
782 pin -= pctl->desc->pin_base;
783 sunxi_mux_reg(pctl, pin, ®, &shift, &mask);
785 raw_spin_lock_irqsave(&pctl->lock, flags);
787 writel((readl(pctl->membase + reg) & ~mask) | config << shift,
788 pctl->membase + reg);
790 raw_spin_unlock_irqrestore(&pctl->lock, flags);
797 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
798 struct sunxi_pinctrl_group *g = pctl->groups + group;
799 struct sunxi_pinctrl_function *func = pctl->functions + function;
801 sunxi_pinctrl_desc_find_function_by_name(pctl,
819 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
828 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
839 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
841 unsigned short bank_offset = bank - pctl->desc->pin_base /
843 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
848 if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators)))
857 reg = regulator_get(pctl->dev, supply);
859 return dev_err_probe(pctl->dev, PTR_ERR(reg),
865 dev_err(pctl->dev,
870 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
885 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
887 unsigned short bank_offset = bank - pctl->desc->pin_base /
889 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
915 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
917 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
923 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
924 bool set_mux = pctl->desc->irq_read_needs_mux &&
929 sunxi_data_reg(pctl, offset, ®, &shift, &mask);
932 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
934 val = (readl(pctl->membase + reg) & mask) >> shift;
937 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
945 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
949 sunxi_data_reg(pctl, offset, ®, &shift, &mask);
951 raw_spin_lock_irqsave(&pctl->lock, flags);
953 val = readl(pctl->membase + reg);
960 writel(val, pctl->membase + reg);
962 raw_spin_unlock_irqrestore(&pctl->lock, flags);
968 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
971 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
995 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
997 unsigned pinnum = pctl->desc->pin_base + offset;
1003 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
1012 return irq_find_mapping(pctl->domain, irqnum);
1017 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1021 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
1022 pctl->irq_array[d->hwirq], "irq");
1026 ret = gpiochip_lock_as_irq(pctl->chip,
1027 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1029 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
1035 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
1042 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1044 gpiochip_unlock_as_irq(pctl->chip,
1045 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1050 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1051 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
1077 raw_spin_lock_irqsave(&pctl->lock, flags);
1086 regval = readl(pctl->membase + reg);
1088 writel(regval | (mode << index), pctl->membase + reg);
1090 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1097 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1098 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1102 writel(1 << status_idx, pctl->membase + status_reg);
1107 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1108 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1113 raw_spin_lock_irqsave(&pctl->lock, flags);
1116 val = readl(pctl->membase + reg);
1117 writel(val & ~(1 << idx), pctl->membase + reg);
1119 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1124 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1125 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1130 raw_spin_lock_irqsave(&pctl->lock, flags);
1133 val = readl(pctl->membase + reg);
1134 writel(val | (1 << idx), pctl->membase + reg);
1136 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1147 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1150 return irq_set_irq_wake(pctl->irq[bank], on);
1190 struct sunxi_pinctrl *pctl = d->host_data;
1198 pin = pctl->desc->pin_base + base + intspec[1];
1200 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1218 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1221 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1222 if (irq == pctl->irq[bank])
1225 WARN_ON(bank == pctl->desc->irq_banks);
1229 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1230 val = readl(pctl->membase + reg);
1236 generic_handle_domain_irq(pctl->domain,
1243 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1246 struct sunxi_pinctrl_function *func = pctl->functions;
1260 pctl->nfunctions++;
1267 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1282 pctl->groups = devm_kcalloc(&pdev->dev,
1283 pctl->desc->npins, sizeof(*pctl->groups),
1285 if (!pctl->groups)
1288 for (i = 0; i < pctl->desc->npins; i++) {
1289 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1290 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1292 if (pin->variant && !(pctl->variant & pin->variant))
1299 pctl->ngroups++;
1308 pctl->functions = kcalloc(7 * pctl->ngroups + 4,
1309 sizeof(*pctl->functions),
1311 if (!pctl->functions)
1315 for (i = 0; i < pctl->desc->npins; i++) {
1316 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1319 if (pin->variant && !(pctl->variant & pin->variant))
1323 if (func->variant && !(pctl->variant & func->variant))
1329 pctl->irq_array[irqnum] = pin->pin.number;
1332 sunxi_pinctrl_add_function(pctl, func->name);
1337 ptr = krealloc(pctl->functions,
1338 pctl->nfunctions * sizeof(*pctl->functions),
1341 kfree(pctl->functions);
1342 pctl->functions = NULL;
1345 pctl->functions = ptr;
1347 for (i = 0; i < pctl->desc->npins; i++) {
1348 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1351 if (pin->variant && !(pctl->variant & pin->variant))
1358 if (func->variant && !(pctl->variant & func->variant))
1361 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1364 kfree(pctl->functions);
1375 kfree(pctl->functions);
1413 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1430 losc = devm_clk_get(pctl->dev, "losc");
1434 hosc = devm_clk_get(pctl->dev, "hosc");
1438 for (i = 0; i < pctl->desc->irq_banks; i++) {
1468 pctl->membase +
1469 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1482 struct sunxi_pinctrl *pctl;
1487 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1488 if (!pctl)
1490 platform_set_drvdata(pdev, pctl);
1492 raw_spin_lock_init(&pctl->lock);
1494 pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1495 if (IS_ERR(pctl->membase))
1496 return PTR_ERR(pctl->membase);
1498 pctl->dev = &pdev->dev;
1499 pctl->desc = desc;
1500 pctl->variant = variant;
1501 if (pctl->variant >= PINCTRL_SUN20I_D1) {
1502 pctl->bank_mem_size = D1_BANK_MEM_SIZE;
1503 pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
1504 pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
1506 pctl->bank_mem_size = BANK_MEM_SIZE;
1507 pctl->pull_regs_offset = PULL_REGS_OFFSET;
1508 pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
1511 pctl->irq_array = devm_kcalloc(&pdev->dev,
1512 IRQ_PER_BANK * pctl->desc->irq_banks,
1513 sizeof(*pctl->irq_array),
1515 if (!pctl->irq_array)
1525 pctl->desc->npins, sizeof(*pins),
1530 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1531 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1533 if (pin->variant && !(pctl->variant & pin->variant))
1548 pctrl_desc->npins = pctl->ngroups;
1562 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1563 if (IS_ERR(pctl->pctl_dev)) {
1565 return PTR_ERR(pctl->pctl_dev);
1568 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1569 if (!pctl->chip)
1572 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1573 pctl->chip->owner = THIS_MODULE;
1574 pctl->chip->request = gpiochip_generic_request;
1575 pctl->chip->free = gpiochip_generic_free;
1576 pctl->chip->set_config = gpiochip_generic_config;
1577 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1578 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1579 pctl->chip->get = sunxi_pinctrl_gpio_get;
1580 pctl->chip->set = sunxi_pinctrl_gpio_set;
1581 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1582 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1583 pctl->chip->of_gpio_n_cells = 3;
1584 pctl->chip->can_sleep = false;
1585 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1586 pctl->desc->pin_base;
1587 pctl->chip->label = dev_name(&pdev->dev);
1588 pctl->chip->parent = &pdev->dev;
1589 pctl->chip->base = pctl->desc->pin_base;
1591 ret = gpiochip_add_data(pctl->chip, pctl);
1595 for (i = 0; i < pctl->desc->npins; i++) {
1596 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1598 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1599 pin->pin.number - pctl->desc->pin_base,
1616 pctl->irq = devm_kcalloc(&pdev->dev,
1617 pctl->desc->irq_banks,
1618 sizeof(*pctl->irq),
1620 if (!pctl->irq) {
1625 for (i = 0; i < pctl->desc->irq_banks; i++) {
1626 pctl->irq[i] = platform_get_irq(pdev, i);
1627 if (pctl->irq[i] < 0) {
1628 ret = pctl->irq[i];
1633 pctl->domain = irq_domain_add_linear(node,
1634 pctl->desc->irq_banks * IRQ_PER_BANK,
1636 pctl);
1637 if (!pctl->domain) {
1643 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1644 int irqno = irq_create_mapping(pctl->domain, i);
1650 irq_set_chip_data(irqno, pctl);
1653 for (i = 0; i < pctl->desc->irq_banks; i++) {
1655 writel(0, pctl->membase +
1656 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1658 pctl->membase +
1659 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1661 irq_set_chained_handler_and_data(pctl->irq[i],
1663 pctl);
1666 sunxi_pinctrl_setup_debounce(pctl, node);
1675 gpiochip_remove(pctl->chip);