pinctrl/starfive/pinctrl-starfive-jh7110.c

99 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
100 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
104 	if (pin < sfp->gc.ngpio) {
107 		u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
108 		u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
109 		u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
127 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
128 	struct device *dev = sfp->gc.parent;
152 	mutex_lock(&sfp->mutex);
230 	mutex_unlock(&sfp->mutex);
240 	mutex_unlock(&sfp->mutex);
253 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
256 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
268 	reg_dout = sfp->base + info->dout_reg_base + offset;
269 	reg_doen = sfp->base + info->doen_reg_base + offset;
276 		reg_din = sfp->base + info->gpi_reg_base + ioffset;
283 	raw_spin_lock_irqsave(&sfp->lock, flags);
292 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
299 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
300 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
314 			info->jh7110_set_one_pin_mux(sfp,
351 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
354 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
362 	padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
366 	reg = sfp->base + padcfg_base + 4 * pin;
369 	raw_spin_lock_irqsave(&sfp->lock, flags);
372 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
378 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
379 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
388 	padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
392 	padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
448 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
512 		jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value);
521 	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
522 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
529 	padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
533 	value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
551 	struct jh7110_pinctrl *sfp = container_of(gc,
553 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
556 	u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
567 	struct jh7110_pinctrl *sfp = container_of(gc,
569 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
572 	jh7110_padcfg_rmw(sfp, gpio,
577 		info->jh7110_set_one_pin_mux(sfp, gpio,
586 	struct jh7110_pinctrl *sfp = container_of(gc,
588 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
591 		info->jh7110_set_one_pin_mux(sfp, gpio,
596 	jh7110_padcfg_rmw(sfp, gpio,
604 	struct jh7110_pinctrl *sfp = container_of(gc,
606 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
607 	void __iomem *reg = sfp->base + info->gpioin_reg_base
616 	struct jh7110_pinctrl *sfp = container_of(gc,
618 	const struct jh7110_pinctrl_soc_info *info = sfp->info;
621 	void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
626 	raw_spin_lock_irqsave(&sfp->lock, flags);
629 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
635 	struct jh7110_pinctrl *sfp = container_of(gc,
672 	jh7110_padcfg_rmw(sfp, gpio, mask, value);
678 	struct jh7110_pinctrl *sfp = container_of(gc,
681 	sfp->gpios.name = sfp->gc.label;
682 	sfp->gpios.base = sfp->gc.base;
683 	sfp->gpios.pin_base = 0;
684 	sfp->gpios.npins = sfp->gc.ngpio;
685 	sfp->gpios.gc = &sfp->gc;
686 	pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
692 	struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
693 	const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
695 	void __iomem *ic = sfp->base + irq_reg->ic_reg_base
701 	raw_spin_lock_irqsave(&sfp->lock, flags);
705 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
710 	struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
711 	const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
713 	void __iomem *ie = sfp->base + irq_reg->ie_reg_base
719 	raw_spin_lock_irqsave(&sfp->lock, flags);
722 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
724 	gpiochip_disable_irq(&sfp->gc, d->hwirq);
729 	struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
730 	const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
732 	void __iomem *ie = sfp->base + irq_reg->ie_reg_base
734 	void __iomem *ic = sfp->base + irq_reg->ic_reg_base
740 	raw_spin_lock_irqsave(&sfp->lock, flags);
747 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
752 	struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
753 	const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
755 	void __iomem *ie = sfp->base + irq_reg->ie_reg_base
761 	gpiochip_enable_irq(&sfp->gc, d->hwirq);
763 	raw_spin_lock_irqsave(&sfp->lock, flags);
766 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
771 	struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
772 	const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
774 	void __iomem *base = sfp->base + 4 * (gpio / 32);
814 	raw_spin_lock_irqsave(&sfp->lock, flags);
823 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
846 	struct jh7110_pinctrl *sfp;
861 	sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
862 	if (!sfp)
866 	sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
867 				       sizeof(*sfp->saved_regs), GFP_KERNEL);
868 	if (!sfp->saved_regs)
872 	sfp->base = devm_platform_ioremap_resource(pdev, 0);
873 	if (IS_ERR(sfp->base))
874 		return PTR_ERR(sfp->base);
917 	sfp->info = info;
918 	sfp->dev = dev;
919 	platform_set_drvdata(pdev, sfp);
920 	sfp->gc.parent = dev;
921 	raw_spin_lock_init(&sfp->lock);
922 	mutex_init(&sfp->mutex);
926 					     sfp, &sfp->pctl);
931 	sfp->gc.label = dev_name(dev);
932 	sfp->gc.owner = THIS_MODULE;
933 	sfp->gc.request = pinctrl_gpio_request;
934 	sfp->gc.free = pinctrl_gpio_free;
935 	sfp->gc.get_direction = jh7110_gpio_get_direction;
936 	sfp->gc.direction_input = jh7110_gpio_direction_input;
937 	sfp->gc.direction_output = jh7110_gpio_direction_output;
938 	sfp->gc.get = jh7110_gpio_get;
939 	sfp->gc.set = jh7110_gpio_set;
940 	sfp->gc.set_config = jh7110_gpio_set_config;
941 	sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
942 	sfp->gc.base = info->gc_base;
943 	sfp->gc.ngpio = info->ngpios;
945 	jh7110_irq_chip.name = sfp->gc.label;
946 	gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
947 	sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
948 	sfp->gc.irq.num_parents = 1;
949 	sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
950 					   sizeof(*sfp->gc.irq.parents),
952 	if (!sfp->gc.irq.parents)
954 	sfp->gc.irq.default_type = IRQ_TYPE_NONE;
955 	sfp->gc.irq.handler = handle_bad_irq;
956 	sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
961 	sfp->gc.irq.parents[0] = ret;
963 	ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
967 	dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
969 	return pinctrl_enable(sfp->pctl);
975 	struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
979 	raw_spin_lock_irqsave(&sfp->lock, flags);
980 	for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
981 		sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);
983 	raw_spin_unlock_irqrestore(&sfp->lock, flags);
989 	struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
993 	raw_spin_lock_irqsave(&sfp->lock, flags);
994 	for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
995 		writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
997 	raw_spin_unlock_irqrestore(&sfp->lock, flags);