pinctrl/samsung/pinctrl-exynos.c

54 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
59 	if (bank->eint_mask_offset)
60 		reg_mask = bank->pctl_offset + bank->eint_mask_offset;
62 		reg_mask = our_chip->eint_mask + bank->eint_offset;
64 	raw_spin_lock_irqsave(&bank->slock, flags);
66 	mask = readl(bank->eint_base + reg_mask);
68 	writel(mask, bank->eint_base + reg_mask);
70 	raw_spin_unlock_irqrestore(&bank->slock, flags);
77 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
80 	if (bank->eint_pend_offset)
81 		reg_pend = bank->pctl_offset + bank->eint_pend_offset;
83 		reg_pend = our_chip->eint_pend + bank->eint_offset;
85 	writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
92 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
108 	if (bank->eint_mask_offset)
109 		reg_mask = bank->pctl_offset + bank->eint_mask_offset;
111 		reg_mask = our_chip->eint_mask + bank->eint_offset;
113 	raw_spin_lock_irqsave(&bank->slock, flags);
115 	mask = readl(bank->eint_base + reg_mask);
117 	writel(mask, bank->eint_base + reg_mask);
119 	raw_spin_unlock_irqrestore(&bank->slock, flags);
126 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
157 	if (bank->eint_con_offset)
158 		reg_con = bank->pctl_offset + bank->eint_con_offset;
160 		reg_con = our_chip->eint_con + bank->eint_offset;
162 	con = readl(bank->eint_base + reg_con);
165 	writel(con, bank->eint_base + reg_con);
173 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
174 	struct samsung_pinctrl_drv_data *d = bank->drvdata;
185 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
186 	const struct samsung_pin_bank_type *bank_type = bank->type;
191 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
193 		dev_err(bank->gpio_chip.parent,
195 			bank->name, irqd->hwirq);
199 	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
203 	raw_spin_lock_irqsave(&bank->slock, flags);
205 	con = readl(bank->pctl_base + reg_con);
208 	writel(con, bank->pctl_base + reg_con);
210 	raw_spin_unlock_irqrestore(&bank->slock, flags);
217 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
218 	const struct samsung_pin_bank_type *bank_type = bank->type;
222 	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
226 	raw_spin_lock_irqsave(&bank->slock, flags);
228 	con = readl(bank->pctl_base + reg_con);
231 	writel(con, bank->pctl_base + reg_con);
233 	raw_spin_unlock_irqrestore(&bank->slock, flags);
235 	gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
280 	struct samsung_pin_bank *bank = d->pin_banks;
284 	if (bank->eint_con_offset)
285 		svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
287 		svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
293 	bank += (group - 1);
295 	ret = generic_handle_domain_irq(bank->irq_domain, pin);
315 	struct samsung_pin_bank *bank;
332 	bank = d->pin_banks;
333 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
334 		if (bank->eint_type != EINT_TYPE_GPIO)
337 		bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
338 					   sizeof(*bank->irq_chip), GFP_KERNEL);
339 		if (!bank->irq_chip) {
343 		bank->irq_chip->chip.name = bank->name;
345 		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
346 				bank->nr_pins, &exynos_eint_irqd_ops, bank);
347 		if (!bank->irq_domain) {
353 		bank->soc_priv = devm_kzalloc(d->dev,
355 		if (!bank->soc_priv) {
356 			irq_domain_remove(bank->irq_domain);
366 	for (--i, --bank; i >= 0; --i, --bank) {
367 		if (bank->eint_type != EINT_TYPE_GPIO)
369 		irq_domain_remove(bank->irq_domain);
379 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
380 	unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
383 		irqd->irq, bank->name, irqd->hwirq);
401 			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
423 			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
533 	struct samsung_pin_bank *bank = eintd->bank;
538 	generic_handle_domain_irq(bank->irq_domain, eintd->irq);
587 	struct samsung_pin_bank *bank;
608 	bank = d->pin_banks;
609 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
610 		if (bank->eint_type != EINT_TYPE_WKUP)
613 		bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
615 		if (!bank->irq_chip) {
619 		bank->irq_chip->chip.name = bank->name;
621 		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
622 				bank->nr_pins, &exynos_eint_irqd_ops, bank);
623 		if (!bank->irq_domain) {
629 		if (!fwnode_property_present(bank->fwnode, "interrupts")) {
630 			bank->eint_type = EINT_TYPE_WKUP_MUX;
636 					  bank->nr_pins, sizeof(*weint_data),
643 		for (idx = 0; idx < bank->nr_pins; ++idx) {
644 			irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
647 							bank->name, idx);
651 			weint_data[idx].bank = bank;
679 	bank = d->pin_banks;
681 	for (i = 0; i < d->nr_banks; ++i, ++bank) {
682 		if (bank->eint_type != EINT_TYPE_WKUP_MUX)
685 		muxed_data->banks[idx++] = bank;
693 				struct samsung_pin_bank *bank)
695 	struct exynos_eint_gpio_save *save = bank->soc_priv;
696 	const void __iomem *regs = bank->eint_base;
699 						+ bank->eint_offset);
701 						+ 2 * bank->eint_offset);
703 						+ 2 * bank->eint_offset + 4);
704 	save->eint_mask = readl(regs + bank->irq_chip->eint_mask
705 						+ bank->eint_offset);
707 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
708 	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
709 	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
710 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
714 					    struct samsung_pin_bank *bank)
716 	struct exynos_eint_gpio_save *save = bank->soc_priv;
717 	const void __iomem *regs = bank->eint_base;
719 	save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
720 	save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
722 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
723 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
728 	struct samsung_pin_bank *bank = drvdata->pin_banks;
732 	for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
733 		if (bank->eint_type == EINT_TYPE_GPIO) {
734 			if (bank->eint_con_offset)
735 				exynosauto_pinctrl_suspend_bank(drvdata, bank);
737 				exynos_pinctrl_suspend_bank(drvdata, bank);
739 		else if (bank->eint_type == EINT_TYPE_WKUP) {
741 				irq_chip = bank->irq_chip;
751 				struct samsung_pin_bank *bank)
753 	struct exynos_eint_gpio_save *save = bank->soc_priv;
754 	void __iomem *regs = bank->eint_base;
756 	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
758 			+ bank->eint_offset), save->eint_con);
759 	pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
761 			+ 2 * bank->eint_offset), save->eint_fltcon0);
762 	pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
764 			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
765 	pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
766 			readl(regs + bank->irq_chip->eint_mask
767 			+ bank->eint_offset), save->eint_mask);
770 						+ bank->eint_offset);
772 						+ 2 * bank->eint_offset);
774 						+ 2 * bank->eint_offset + 4);
775 	writel(save->eint_mask, regs + bank->irq_chip->eint_mask
776 						+ bank->eint_offset);
780 					   struct samsung_pin_bank *bank)
782 	struct exynos_eint_gpio_save *save = bank->soc_priv;
783 	void __iomem *regs = bank->eint_base;
785 	pr_debug("%s:     con %#010x => %#010x\n", bank->name,
786 		 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
787 	pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
788 		 readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
790 	writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
791 	writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
796 	struct samsung_pin_bank *bank = drvdata->pin_banks;
799 	for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
800 		if (bank->eint_type == EINT_TYPE_GPIO) {
801 			if (bank->eint_con_offset)
802 				exynosauto_pinctrl_resume_bank(drvdata, bank);
804 				exynos_pinctrl_resume_bank(drvdata, bank);